Power management in high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 1, 1999, Pages 7-15

  Lakshminarayana, Ganesh ^b   Raghunathan, Anand ^a,b   Jha, Niraj K ^a,c   Dey, Sujit ^a,d  

^a IEEE

^b NEC LABORATORIES AMERICA   (United States)

^c Princeton University   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital system design; High level synthesis; Power management; Register sharing

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS;

POWER MANAGEMENT; REGISTER SHARING;

VLSI CIRCUITS;

EID: 0033097603     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.748195     Document Type: Article

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