An efficient algorithm for performance-optimal FPGA technology mapping with retiming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 9, 1998, Pages 738-748

  Cong, Jason ^a   Wu, Chang ^a  

^a University of California   (United States)

Author keywords

Expanded circuit; Field programmable gate array (fpga); Lookup table; Retiming; Technology mapping

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; ITERATIVE METHODS; TABLE LOOKUP;

MAPPING ALGORITHM; RETIMING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032163099     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.720312     Document Type: Article

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