Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 726-729

  Cong, Jason ^a   Hwang, Yean Yow ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; TABLE LOOKUP;

DECOMPOSITION ALGORITHM; FIELD PROGRAMMABLE GATE ARRAYS (FPGAS); K BOUNDED NETWORKS; MAPPING DEPTH;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0029707981     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240656     Document Type: Conference Paper

References (10)