Graph-based FPGA technology mapping for delay optimization

IEEE Design and Test of Computers

Volumn 9, Issue 3, 1992, Pages 7-20

  Chen, Kuang Chien ^a   Cong, Jason ^b   Ding, Yuzheng ^b   Kahng, Andrew B ^b   Trajmar, Peter ^b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84948591324     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.156154     Document Type: Article

References (21)

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