SCOPUS 정보 검색 플랫폼

Volumn 6, Issue 1-6, 1991, Pages 5-35

Retiming synchronous circuitry

(2) Leiserson, Charles E a Saxe, James B b

a MASSACHUSETTS INSTITUTE OF TECHNOLOGY (United States)

b HEWLETT PACKARD COMPANY (United States)

Author keywords

Digital circuitry; Graph theory; Linear programming; Network flow; Optimization; Pipelining; Propagation delay; Retiming; Synchronous circuitry; Systolic circuits; Timing analysis

Indexed keywords

COMPUTER SYSTEMS, DIGITAL - PIPELINE PROCESSING; INTEGRATED CIRCUITS, VLSI - DESIGN; LOGIC DESIGN; MATHEMATICAL PROGRAMMING, LINEAR; MATHEMATICAL TECHNIQUES - GRAPH THEORY;

PIPELINE ARCHITECTURE; SYNCHRONOUS CIRCUITRY; SYSTOLIC CIRCUITS;

INTEGRATED CIRCUITS, DIGITAL;

EID: 33746763910 PISSN: 01784617 EISSN: 14320541 Source Type: Journal
DOI: 10.1007/BF01759032 Document Type: Article

Times cited : (228)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.