FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 1, 1994, Pages 1-12

  Cong, Jason ^a   Ding, Yuzheng ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; CONFORMAL MAPPING; ELECTRIC NETWORK SYNTHESIS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTIMIZATION; POLYNOMIALS; TABLE LOOKUP;

BOOLEAN NETWORKS; DELAY OPTIMIZATION; DEPTH MINIMIZATION; FIELD PROGRAMMABLE GATE ARRAY; FLOWMAP; HEURISTIC ALGORITHMS; NETWORK FLOW COMPUTATION; OPTIMAL SOLUTION; OPTIMAL TECHNOLOGY MAPPING ALGORITHM; POLYNOMIAL TIME;

COMPUTER AIDED LOGIC DESIGN;

EID: 0028259317     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.273754     Document Type: Article

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