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Volumn , Issue , 1993, Pages 213-128
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On area/depth trade-off in LUT-based FPGA technology mapping
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
MAPPING;
OPTIMIZATION;
TABLE LOOKUP;
TECHNOLOGY;
FIELD PROGRAMMABLE GATE ARRAYS;
TECHNOLOGY MAPPING;
VLSI CIRCUITS;
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EID: 0027307171
PISSN: 01467123
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/157485.164675 Document Type: Conference Paper |
Times cited : (36)
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References (16)
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