Routability-Driven Technology Mapping for Lookup Table-Based FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 1, 1994, Pages 13-26

  Kong, Jackson ^b   Chan, Pak K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Washington Hospital Healthcare System   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; CONFORMAL MAPPING; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; TABLE LOOKUP;

COMPACT DESIGNS; CONFIGURABLE LOGIC BLOCKS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC CELL ARRAYS; ROUTABILITY; SOFTWARE PACKAGE RMAP; TECHNOLOGY MAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0028341924     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.273753     Document Type: Article

References (28)

1. K. A. El-Ayat, A. El Gamal, R. Guo, J. Chang, R. K. Mak, F. Chiu, E. Z. Hamdy, J. McCollum, and A. Mohsen, “A CMOS electrically configurable gate array,” IEEE J. Solid-State Circuits, vol. 24, pp. 752–762, June 1989.
2. Xilinx Inc., XILINX: The Programmable Gate Array Data Book, San Jose, CA, 1992.
3. R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, Vincentelli, “Logic synthesis for programmable gate arrays,” in ACM IEEE 27th Design Automation Conf. Proc., Orlando, FL, June 1990, pp. 620–625.
4. R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Improved logic synthesis algorithms for table look up architectures,” in IEEE Int. Conf. Computer-Aided Design ICCAD-91, Santa Clara, CA, Nov. 1991, pp. 564–567.
5. N.- S. Woo, “A heuristic method for FPGA technology mapping based on the edge visibility,” in ACM IEEE 28th Design Automation Conf. Proc., San Francisco, CA, June 1991, 248-251.
6. R. J. Francis, J. Rose, and K. Chung, “Chortle: A technology mapping program for lookup table-based field programmable gate arrays,” in ACM IEEE 27th Design Automation Conf. Proc., Orlando, FL, June 1990, pp. 613–619.
7. R. J. Francis, J. Rose, and Z. Vranesic, “Chortle-crf: Fast technology mapping for lookup table-based FPGA’s,” in ACM IEEE 28th Design Automation Conf. Proc., San Francisco, CA, June 1991, pp. 227–233.
8. F. Dresig, O. Rettig, and U. G. Baitinger, “Logic synthesis for universal logic cells,” in Proc. Int. Workshop on Field Programmable Logic and Applications, Oxford, England, Sept. 4-6, 1991.
9. D. Filo, J. Yang, F. Mailhot, and G. De Micheli, “Technology Mapping for a Two-Output RAM-based Field-Programmable Gate Arrays,” in European Design Automation Conf., Feb. 1991, pp. 534–538.
10. J. Rose and S. Brown, “Flexibility of interconnection structures for field-programmable programmable gate arrays,” IEEE J. Solid-State Circuits, vol. 26, pp. 277–282, Mar. 1991.
11. Xilinx Inc., XILINX Application Note: Fundamentals of Placement and Routing. San Jose, CA, 1990.
12. A. El Gamal, “Two-dimensional stochastic model for interconnections in master slice integrated circuits,” IEEE Tran. Circuits and Systems, vol. 28, pp. 127–138, Feb. 1981.
13. S. Sastry and A. C. Parker, “Stochastic models for wireability analysis of gate arrays,” IEEE Tran. Computer-Aided Design, vol. CAD-5, pp. 52–65, Jan. 1986.
14. C. M. Fiduccia and R. Mattheyses, “A linear-time heuristic for improving network partitions,” in ACM IEEE 19th Design Automation Conf Proc., Las Vegas, NV, June 1982, pp. 175–181.
15. S. Trimberger and M. R. Chene, “Placement-based partitioning for lookup-table-based field programmable gate arrays,” in Proc. 1st Int. ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Berkeley, CA, Feb. 1992, pp. 137–142.
16. N. Bhat and D. Hill, “Routable technology mapping for LUT FPGA’s,” in 1992 IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, Oct. 1992 pp. 95–98.
17. M. Feuer, “Connectivity of random logic,” IEEE Trans. Computers, vol. C-31, pp. 29–33, Jan. 1982.
18. R. J. Francis, J. Rose, and Z. Vranesic, “Technology mapping for lookup table-based FPGA's for performance,” in IEEE Int. Conf. on Computer-Aided Design ICCAD-91, Santa Clara, CA, Nov. 1991, pp. 568–571.
19. Xilinx Inc., XILINX 2000/3000 Development System Reference Guide. San Jose, CA, 1991.
20. S. Trimberger, personal communication, Sept. 1992.
21. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, “MIS: A multiple-level logic optimization system,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1062–1081, Nov. 1987.
22. K. Karplus, “Xmap: A technology mapper for table-lookup field programmable gate arrays,” in ACM IEEE 28th Design Automation Conf. Proc., San Francisco, CA, June 1991, pp. 240–243.
23. E. Logic, EXEMPLAR: XNFOPT. Berkeley, CA, 1990.
24. J. Kong, “A Routability Driven Technology Mapper for Table-Lookup Based Field-programmable Gate-Arrays,” Master's thesis, Board of Studies in Computer Engineering, University of California at Santa Cruz, 1992.
25. R. Francis, personal communication, Aug. 1991.
26. S. Devadas, H. K. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, telli, “MUSTANG: State assignment of finite state machines targeting multilevel logic implementations,” IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 1290–1299, Dec. 1988.
27. P. K. Chan, M. Schlag, and J. Zien, “On routability prediction for field-programmable programmable gate arrays,” in ACM IEEE 30th Design Automation Conf. Proc., Dallas, TX, June 1993, pp. 326–330.
28. D. D. Hill, B. K. Britton, N.- S. Woo, S. Singh, T. Poon, and B. Krambeck, “A new architecture for high-performance FPGA's" in 1992 Int. Workshop on Field Programmable Logic and Applications, Vienna, Austria, September 1992.