Maple: a simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 156-163

  Togawa, Nozomu ^a   Sato, Masao ^a   Ohtsuki, Tatsuo ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; COMPUTER NETWORKS; CONFORMAL MAPPING; FUNCTIONS; GRAPH THEORY; LOGIC CIRCUITS; LOGIC DESIGN; RECURSIVE FUNCTIONS; TABLE LOOKUP;

BENCHMARK CIRCUITS; BOOLEAN NETWORK; COMBINATIONAL FUNCTION; DIRECTED ACYCLIC GRAPH; FIELD PROGRAMMABLE GATE ARRAYS; GLOBAL ROUTING ALGORITHM; LOGIC BLOCKS; MAPPING ALGORITHM; MAPPING WITH LAYOUT EXECUTION; PSEUDO BLOCKS SEQUENCE;

LOGIC GATES;

EID: 0028697847     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (19)