Improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 572-578

  Cong, Jason ^a   Wu, Chang ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CELLULAR ARRAYS; COMPUTATIONAL COMPLEXITY; HEURISTIC METHODS; LOGIC GATES; OPTIMIZATION;

MONOTONE PROPERTY; RETIMING; SEQMAPII ALGORITHM;

SEQUENTIAL CIRCUITS;

EID: 0030413605     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)