Optimal clock period fpga technology mapping for sequential circuits

ACM Transactions on Design Automation of Electronic Systems

Volumn 3, Issue 3, 1998, Pages 437-462

  Pan, Reichen ^a,d   Liu, C L ^b,c  

^a CLARKSON UNIVERSITY   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c Clarkson University   (United States)

^d University of Illinois at Urbana Champaign   (United States)

Author keywords

Algorithms; Clock period; Field programmable gate arrays; FPGAs; Logic replication; Look up tables; Performance; Retiming; Sequential synthesis; Technology mapping

Indexed keywords

EID: 22644451539     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/293625.293632     Document Type: Article

References (30)

1. ALTERA. 1995. Data Book. Altéra, San Jose, CA.
2. BHAT, N., HILL, D. 1992. Routable technology mapping for FPGAs. In Proceedings of the ACM/SIGDA Workshop on FPGAs, 143-148.
3. CONG, J., DING, Y. 1993. Beyond the combinational limit in depth minimization for LUT-based FPGA designs. In Proceedings of the Digest IEEE/ACM International Conference on Computer-Aided Design 110-114.
4. CONG, J., DING, Y. 1994. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans, on Computer-Aided Design 13, 1-11.
5. GONG, J., DING, Y. 1994. On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans, on VLSI Systems 2, 137-148.
6. CoNG, J., Wu, C. 1996. An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design. In Proceedings of the International Conference on Computer Design, 572-578.
7. CONG, J., Wu, C. 1997. Performance-driven FPGA synthesis with retiming and pipelining for sequential circuits. In Proceedings of the ACMI IEEE Design Automation Conference.
8. CORMEN, T. H., LEISERSON, C. E., RIVEST, R. L. 1990. Introduction to Algorithms. McGraw-Hill Book Company, New York.
9. FARRAHI, A. H., SARRAFZADEH, M. 1994. Complexity of the lookup-table minimization problem for FPGA technology mapping. IEEE Trans, on Computer-Aided Design 13, 1319-1332.
10. FRANCIS, R. J., ROSE, J., CHUNG, K. 1990. Chortle: A technology mapping for lookup table-based field programmable gate arrays. In Proceedings of the ACM/IEEE Design Automation Conference, 613-619.
11. FRANCIS, R. J., ROSE, J., VRANESIC, Z. 1991. Chortle-erf: Fast technology mapping for lookup table-based FPGAs. In Proceedings of the ACMI IEEE Design Automation Conference, 227-233.
12. FRANCIS, R. J., ROSE, J., VRANESIC, Z. 1991. Technology mapping for lookup table-based FPGAs for performance. In Digest of the IEEE I ACM International Conference on Computer-Aided Design, 568-571.
13. KARPLUS, K. 1991. Xmap: A technology mapper for table-lookup FPGAs. In Proceedings of the ACMI IEEE Design Automation Conference, 240-243.
14. LEISERSON, C. E., SAXE, J. B. 1991. Retiming synchronous circuitry. Algorithmica 6, 5-35.
15. MATHUR, A., LlU, C. L. 1994. Performance driven technology mapping for lookup-table based FPGAs using the general delay model. In Proceedings of the ACM/SIGDA Workshop on Field Programmable Gate Arrays.
16. AT&T MICROELECTRONICS. 1995. AT&T Field-Programmable Gate Arrays Data Book. AT&T Microelectronics.
17. MURGAI, R., BRAYTON, R., SANGIOVANNI-VINCENTELLI, A. 1993. Sequential synthesis for table look up programmable gate arrays. In Proceedings of the ACMI IEEE Design Automation Conference, 224-229.
18. MURGAI, R., NISHIZAKI, Y., SHENOY, N., BRAYTON, R., SANGIOVANNI-VINCENTELLI, A. 1990. Logic synthesis algorithms for table look up programmable gate arrays. In Proceedings of the ACM/IEEE Design Automation Conference, 620-625.
19. MURGAI, R., SHENOY, N., BRAYTON, R., SANGIOVANNI-VINCENTELLI, A. 1991. Improved logic synthesis algorithms for table look up architectures. In Digest of the IEEEIACM International Conference on Computer-Aided Design, 564-567.
20. PAN, P. To appear. Continuous retiming: algorithms and applications. In International Conference on Computer Design (ICCD).
21. PAN, P., Liu, C. L. 1996. Optimal clock period FPGA technology mapping for sequential circuits. In Proceedings of the ACMI IEEE Design Automation Conference (DAC), 720-725.
22. PAN, P., Liu, C. L. 1996. Technology mapping of sequential circuits for LUT-based FPGAs for performance. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 58-64.
23. SAWKAR, P., THOMAS, D. 1992. Area and delay mapping for table-look-up based field programmable gate arrays. In Proceedings of the ACM/IEEE Design Automation Conference, 368-373.
24. SAWKAR, P., THOMAS, D. 1993. Performance directed technology mapping for look-up table based FPGAs. In Proceedings of the ACM/IEEE Design Automation Conference, 208-212.
25. SCHLAG, M., KONG, J., CHAN, P. 1994. Routability-driven technology mapping for lookup table-based FPGA's. IEEE Trans, on Computer-Aided Design 13, 13-26.
26. SENTOVICH, E. M., ET AL. 1992. Sequential circuit design using synthesis and optimization. In Proceedings of the International Conference on Computer Design, 328-333.
27. WEINMANN, U., ROSENSTIEL, W. 1993. Technology mapping for sequential circuits based on retiming techniques. In Proceedings of the European Design Automation Conference, 318-323.
28. Woo, N.-S. 1991. A heuristic method for FPGA technology mapping based on the edge visibility. In Proceedings of the ACMI IEEE Design Automation Conference, 248-251.
29. XILINX. 1993. The Programmable Gate Arrays Data Book. Xilinx, San Jose, CA.
30. YANG, H., WONG, D. F. 1994. Edge-Map: Optimal performance driven technology mapping for iterative LUT based FPGA designs. In Digest of the IEEE I ACM International Conference on Computer-Aided Design, 150-155.