Optimal clock period FPGA technology mapping for sequential circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 720-725

  Pan, Peichen ^a   Liu, C L ^a  

^a CLARKSON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER ARCHITECTURE; DELAY CIRCUITS; FLIP FLOP CIRCUITS; LOGIC GATES; OPTIMIZATION; POLYNOMIALS; TIMING CIRCUITS;

CIRCUIT RETIMING; FIELD PROGRAMMABLE GATE ARRAYS (FPGAS); MAPPING ALGORITHM;

SEQUENTIAL CIRCUITS;

EID: 0029720913     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240655     Document Type: Conference Paper

References (18)