-
1
-
-
50149116875
-
"New technologies for compact TFT LCD's with high-aperture ratio," in
-
1990, pp. 315-318.
-
Y. Matueda, M. Ashizawa, S. Aruga, H. Ohshima, and S. Morozumi, "New technologies for compact TFT LCD's with high-aperture ratio," in SID Dig., 1990, pp. 315-318.
-
SID Dig.
-
-
Matueda, Y.1
Ashizawa, M.2
Aruga, S.3
Ohshima, H.4
Morozumi, S.5
-
2
-
-
0029536350
-
"Fabrication of low-temperature bottom-gate poly-Si TFT's on large-area substrate by linear-beam excimer laser crystallization and ion doping method," in
-
1995, p. 829.
-
H. Hayashi, M. Kunii, N. Suzuki, Y. Kanya, M. Kusi, M. Minegishi, T. Urazono, M. Fujino, T. Noguchi, and M. Yamazaki, "Fabrication of low-temperature bottom-gate poly-Si TFT's on large-area substrate by linear-beam excimer laser crystallization and ion doping method," in IEDM Tech. Dig., 1995, p. 829.
-
IEDM Tech. Dig.
-
-
Hayashi, H.1
Kunii, M.2
Suzuki, N.3
Kanya, Y.4
Kusi, M.5
Minegishi, M.6
Urazono, T.7
Fujino, M.8
Noguchi, T.9
Yamazaki, M.10
-
3
-
-
0022119783
-
"Anomalous leakage current in LPCVD polysilicon MOSFET's,"
-
32, pp. 1878-1884, Sept. 1985.
-
J. G. Possum, A. Ortiz-Conde, H. Shichijo, and S. K. Banerjee, "Anomalous leakage current in LPCVD polysilicon MOSFET's," IEEE Trans. Electron Devices, Vol. ED32, pp. 1878-1884, Sept. 1985.
-
IEEE Trans. Electron Devices, Vol. ED
-
-
Possum, J.G.1
Ortiz-Conde, A.2
Shichijo, H.3
Banerjee, S.K.4
-
4
-
-
84949077617
-
"Leakage current mechanisms in hydrogen-passivated fine-grain polycrystalline silicon-on-insulator MOSFET's,"
-
33, pp. 1518-1528, Oct. 1986.
-
S. K. Madan and D. A. Antoniadis, "Leakage current mechanisms in hydrogen-passivated fine-grain polycrystalline silicon-on-insulator MOSFET's," IEEE Trans. Electron Devices, Vol. ED33, pp. 1518-1528, Oct. 1986.
-
IEEE Trans. Electron Devices, Vol. ED
-
-
Madan, S.K.1
Antoniadis, D.A.2
-
5
-
-
0023851207
-
"Characteristics of offset-structure polycrystalline-silicon thin-film transistors,"
-
vol. 9, pp. 23-25, Jan. 1988.
-
K. Tanaka, H. Aral, and S. Kohda, "Characteristics of offset-structure polycrystalline-silicon thin-film transistors," IEEE Electron Device Lett., vol. 9, pp. 23-25, Jan. 1988.
-
IEEE Electron Device Lett.
-
-
Tanaka, K.1
Aral, H.2
Kohda, S.3
-
6
-
-
0023421569
-
"Leakage current characteristics of offset-gate-structure polycrystalline-silicon MOSFET's,"
-
8, pp. 434-436, Sept. 1987.
-
S. Seki, O. Kogure, and B. Tsujiyama, "Leakage current characteristics of offset-gate-structure polycrystalline-silicon MOSFET's," IEEE Electron Device Lett., Vol. EDL8, pp. 434-436, Sept. 1987.
-
IEEE Electron Device Lett., Vol. EDL
-
-
Seki, S.1
Kogure, O.2
Tsujiyama, B.3
-
7
-
-
0029309425
-
"A novel offset gated polysilicon thin film transistor without an additional offset mask,"
-
vol. 16, pp. 161-163, May 1995.
-
B. H. Min, C. M. Park, and M. K. Han, "A novel offset gated polysilicon thin film transistor without an additional offset mask," IEEE Electron Device Lett., vol. 16, pp. 161-163, May 1995.
-
IEEE Electron Device Lett.
-
-
Min, B.H.1
Park, C.M.2
Han, M.K.3
-
8
-
-
0025446609
-
"A simpler 100-V polysilicon TFT with improved turn-on characteristics,"
-
vol. 11, pp. 244-246, June 1990.
-
T. Y. Huang, I.-W. Wu, A. G. Lewis, A. Chiang, and R. H. Bruce, "A simpler 100-V polysilicon TFT with improved turn-on characteristics," IEEE Electron Device Lett., vol. 11, pp. 244-246, June 1990.
-
IEEE Electron Device Lett.
-
-
Huang, T.Y.1
Wu, I.-W.2
Lewis, A.G.3
Chiang, A.4
Bruce, R.H.5
-
9
-
-
0025521006
-
"Device sensitivity of field-plated polysilicon high-voltage TFT's and their application to low-voltage operation,"
-
vol. 11, pp. 541-543, Nov. 1990.
-
_, "Device sensitivity of field-plated polysilicon high-voltage TFT's and their application to low-voltage operation," IEEE Electron Device Lett., vol. 11, pp. 541-543, Nov. 1990.
-
IEEE Electron Device Lett.
-
-
-
10
-
-
0030405963
-
"A novel gate-overlapped LDD poly-Si thin film transistor,"
-
vol. 17, pp. 566-568, Dec. 1996.
-
K.-Y. Choi and M. K. Han, "A novel gate-overlapped LDD poly-Si thin film transistor," IEEE Electron Device Lett., vol. 17, pp. 566-568, Dec. 1996.
-
IEEE Electron Device Lett.
-
-
Choi, K.-Y.1
Han, M.K.2
-
11
-
-
33747057852
-
"Low-temperature poly-Si TFT process technology for large glass substrate," in
-
1994 Int. Displ. Res. Conf., Monterey, CA, 1994, pp. 126-127.
-
A. Mimura, Y. Mikami, K. Kuwabara, Y. Mori, M. Nagai, Y. Naegae, and E. Kaneko, "Low-temperature poly-Si TFT process technology for large glass substrate," in Proc. 1994 Int. Displ. Res. Conf., Monterey, CA, 1994, pp. 126-127.
-
Proc.
-
-
Mimura, A.1
Mikami, Y.2
Kuwabara, K.3
Mori, Y.4
Nagai, M.5
Naegae, Y.6
Kaneko, E.7
-
12
-
-
0027560455
-
"A 10-s doping technology for the application of lowtemperature polysilicon TFT's to giant microelectronics,"
-
vol. 40, pp. 513-520, Mar. 1993.
-
A. Mimura, G. Kawachi, T. Aoyama, T. Suzuki, T. Nagae, N. Konishi, and Y. Mochizuki, "A 10-s doping technology for the application of lowtemperature polysilicon TFT's to giant microelectronics," IEEE Trans. Electron Devices, vol. 40, pp. 513-520, Mar. 1993.
-
IEEE Trans. Electron Devices
-
-
Mimura, A.1
Kawachi, G.2
Aoyama, T.3
Suzuki, T.4
Nagae, T.5
Konishi, N.6
Mochizuki, Y.7
-
13
-
-
0030166754
-
"Low-temperature polycrystalline silicon thin-film transistor with silicon nitride ion stopper,"
-
vol. 17, pp. 258-260, June 1996.
-
K. H. Lee, Y. M. Jhon, H. J. Cha, and J. Jang, "Low-temperature polycrystalline silicon thin-film transistor with silicon nitride ion stopper," IEEE Electron Device Lett., vol. 17, pp. 258-260, June 1996.
-
IEEE Electron Device Lett.
-
-
Lee, K.H.1
Jhon, Y.M.2
Cha, H.J.3
Jang, J.4
-
14
-
-
0029379244
-
"Lowtemperature (<600 °C) polysilicon thin film transistors having
-
vol. 16, pp. 376-379, Sept. 1995.
-
L. Pichon, F. Raoult, O. Bonnaud, J. Pinel, and M. Sarret, "Lowtemperature (<600 °C) polysilicon thin film transistors having in situ doped polysilicon source and drain contacts," IEEE Electron Device Lett., vol. 16, pp. 376-379, Sept. 1995.
-
In Situ Doped Polysilicon Source and Drain Contacts," IEEE Electron Device Lett.
-
-
Pichon, L.1
Raoult, F.2
Bonnaud, O.3
Pinel, J.4
Sarret, M.5
-
15
-
-
0029247258
-
"Characteristics of self-induced lightly-doped-drain polycrystalline silicon thin film transistors with liquid-phase deposition SiO2 as gate-insulator and passivation-layer,"
-
vol. 42, pp. 307-314, Feb. 1995.
-
C. F. Yeh, T. Z. Yang, and T. J. Chen, "Characteristics of self-induced lightly-doped-drain polycrystalline silicon thin film transistors with liquid-phase deposition SiO2 as gate-insulator and passivation-layer," IEEE Trans. Electron Devices, vol. 42, pp. 307-314, Feb. 1995.
-
IEEE Trans. Electron Devices
-
-
Yeh, C.F.1
Yang, T.Z.2
Chen, T.J.3
-
16
-
-
0024908311
-
"High-performance TFT's fabricated by XeCl excimer laser annealing of hydrogenated amorphous-silicon film,"
-
vol. 36, pp. 2868-2872, Dec. 1989.
-
K. Sera, F. Okumura, H. Uchida, S. Itoh, S. Kaneko, and K. Hotta, "High-performance TFT's fabricated by XeCl excimer laser annealing of hydrogenated amorphous-silicon film," IEEE Trans. Electron Devices, vol. 36, pp. 2868-2872, Dec. 1989.
-
IEEE Trans. Electron Devices
-
-
Sera, K.1
Okumura, F.2
Uchida, H.3
Itoh, S.4
Kaneko, S.5
Hotta, K.6
-
17
-
-
0001212787
-
"Two-step annealed polycrystalline silicon thin-film transistors,"
-
vol. 80, no. 3, pp. 1883-1190, 1996.
-
K.-Y. Choi and M. K. Han "Two-step annealed polycrystalline silicon thin-film transistors," J. Appl. Phys., vol. 80, no. 3, pp. 1883-1190, 1996.
-
J. Appl. Phys.
-
-
Choi, K.-Y.1
Han, M.K.2
-
18
-
-
0003679027
-
-
2nd ed. New York: McGraw-Hill, 1988, pp. 258-260.
-
S. M. Sze, VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988, pp. 258-260.
-
VLSI Technology
-
-
Sze, S.M.1
-
19
-
-
0000561219
-
"Downstream microwave plasma-enhanced chemical vapor deposition of oxide using tetraethoxysilane,"
-
vol. 68, no. 2, pp. 793-801, 1990.
-
C. S. Pai and C.-P. Chang, "Downstream microwave plasma-enhanced chemical vapor deposition of oxide using tetraethoxysilane," J. Appl. Phys., vol. 68, no. 2, pp. 793-801, 1990.
-
J. Appl. Phys.
-
-
Pai, C.S.1
Chang, C.-P.2
-
20
-
-
0028257775
-
"Structural dimension effects of plasma hydrogénation on low-temperature poly-Si thin-film transistors,"
-
vol. 33, pp. 649-653, 1994.
-
Y. S. Kim, K.-Y. Choi, S. K. Lee, B. H. Min, and M. K. Han, "Structural dimension effects of plasma hydrogénation on low-temperature poly-Si thin-film transistors," Jpn. J. Appl. Phys., vol. 33, pp. 649-653, 1994.
-
Jpn. J. Appl. Phys.
-
-
Kim, Y.S.1
Choi, K.-Y.2
Lee, S.K.3
Min, B.H.4
Han, M.K.5
-
21
-
-
0030086272
-
"Hydrogen passivation on the grain boundary and intragranular defects in various polysilicon thin-film transistors,"
-
vol. 35, pt. IB, no. 2B, pp. 915-918, 1996.
-
K.-Y. Choi, J. S. Yoo, M. K. Han, and Y. S. Kirn, "Hydrogen passivation on the grain boundary and intragranular defects in various polysilicon thin-film transistors," Jpn. J. Appl. Phys., vol. 35, pt. IB, no. 2B, pp. 915-918, 1996.
-
Jpn. J. Appl. Phys.
-
-
Choi, K.-Y.1
Yoo, J.S.2
Han, M.K.3
Kirn, Y.S.4
-
22
-
-
0024176677
-
"High-voltage thin-film transistors for large-area microelectronics," in
-
1988, pp. 252-255.
-
M. Hack, A. Chiang, T. Y. Huang, A. G. Lewis, R. A. Martin, H. Tuan, I. W. Wu, and P. Yap, "High-voltage thin-film transistors for large-area microelectronics," in IEDM Tech. Dig., 1988, pp. 252-255.
-
IEDM Tech. Dig.
-
-
Hack, M.1
Chiang, A.2
Huang, T.Y.3
Lewis, A.G.4
Martin, R.A.5
Tuan, H.6
Wu, I.W.7
Yap, P.8
-
23
-
-
84942738334
-
"High-performance bottomgate poly-Si/SiN TFT's on glass-substrate," in
-
1992, pp. 669-672.
-
K. Shimizu, O. Sugiura, and M. Matsumura, "High-performance bottomgate poly-Si/SiN TFT's on glass-substrate," in IEDM Tech. Dig., 1992, pp. 669-672.
-
IEDM Tech. Dig.
-
-
Shimizu, K.1
Sugiura, O.2
Matsumura, M.3
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