Leakage Current Mechanisms in Hydrogen-Passivated Fine-Grain Polycrystalline Silicon on Insulator MOSFET's

IEEE Transactions on Electron Devices

Volumn 33, Issue 10, 1986, Pages 1518-1528

  Madan, Sudhir K ^a   Antoniadis, Dimitri A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84949077617     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1986.22702     Document Type: Article

References (28)

1. H. W. Lam, “Silicon on insulating substrates—Recent advances,” in IEDM Tech. Dig., pp. 348–351, 1983.
2. Y. Omura, E. Sano, K. Ohwada, K. Hirata, and Y. Sakakibara, “A low power and high-speed submicron buried-channel MOSFET fabricated on the buried oxide,” IEEE Trans. Electron Devices, vol. ED-29, no. 8, pp. 1331–1332, Aug. 1982.
3. K. Imai, H. Uno, and S. Muramoto, “Full isolation technology by porous oxidized silicon and its application to LSIs,” in IEDM Tech. Dig., pp. 376–379, 1981.
4. J. Tihanyi and H. Schlotterer, “Properties of ESFI MOS transistors due to the floating substrate and the finite volume,” IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 1017–1023, Nov. 1975.
5. —, “Influence of the floating substrate potential on the characteristics of ESFI MOS transistors,” Solid-State Electron., vol. 18, pp. 309-314, 1975.
6. H. W. Lam, Z. P. Sobczak, R. F. Pinizzotto, and A. F. Tasch, Jr., “Device fabrication in (100) silicon-on-oxide produced by a scanning CW-laser-induced lateral seeding technique,” IEEE Trans. Electron Devices, vol. ED-29, no. 3, pp. 380–394, Mar. 1982.
7. S. D. S. Malhi, H. Shichijo, S. K. Banerjee, R. Sundarsean, M. Elahy, G. P. Pollack, W. R. Richardson, A. H. Shah, L. R. Hite, R. H. Womack, P. K. Chatterjee, and H. W. Lam, “Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline silicon,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 258–281, Feb. 1985.
8. H. Shichijo, S. D. S. Malhi, P. K. Chatterjee, R. R. Shah, M. A. Douglas, and H. W. Lam, “Characterization of n-channel and p-channel LPCVD polysilicon MOSFET's,” in IEDM Tech. Dig., pp. 202–205, 1983.
9. H. J. Singh, K. C. Saraswat, J. D. Shott, J. P. McVittie, and J. D. Meindl, “Scaling of SOI/PMOS transistors,” in IEDM Tech. Dig., pp. 67–70, 1983.
10. 4 and A1 films on the passivation of poly-Si films,” in Proc. 42nd Ann. Device Research Conf., paper VB-4, 1984.
11. S. D. S. Malhi, R. Karnaugh, A. H. Shah, L. Hite, P. K. Chatterjee, H. E. Davis, S. S. Mahant-Shetti, C. D. Gosmeyer, R. S. Sundare-san, C. E. Chen, H. W. Lam, R. A. Haken, R. F. Pinizzotto, and R. K. Hester, “A VLSI suitable 2 μm stacked CMOS aprocess,” in Proc. 42nd Ann. Device Research Conf., paper VB-1, 1984.
12. H. Shichijo, S. D. S. Malhi, W. F. Richardson, G. P. Pollack, A. H. Shah, L. R. Hite, S. K. Banerjee, M. Elahy, R. Sundaresan, R. H. Womack, H. W. Lam, and P. K. Chatterjee, “Polysilicon Transistors in VLSI MOS memories,” in IEDM Tech. Dig., pp. 228–231, 1984.
13. S. D. S. Malhi, P. K. Chatterjee, R. F. Pinizzotto, H. W. Lam, C. E. C. Chen, H. Shichijo, R. R. Shah, and D. W. Bellevance, “P-channel MOSFET's in LPCVD polysilicon,” IEEE Electron Device Lett., vol. EDL-4, no. 10, pp. 369–371, Oct. 1983.
14. D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, “SUPREM II—A program for IC process modeling and simulation” SEL 78–020 Stanford Electronics Labs., Stanford Univ., June 1978.
15. J. A. Greenfield, S. E. Hansen, and R. W. Dutton, “Two-dimensional analysis for device modeling,” Stanford Electronics Labs., Stanford Univ., Tech. Rep. G-201-7, July 1980.
16. N.C-C. Lu, L. Gerberg, C.-Y. Lu, and J. D. Meindl, “Modeling and optimization of monolithic polycrystalline silicon resistors,” IEEE Trans. Electron Devices, vol. ED-28, no. 7, pp. 818–830, July 1981.
17. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, pp. 470–474.
18. G. W. Taylor, “Subthreshold conduction in MOSFETs,” IEEE Trans. Electron Devices, vol. ED-25, no. 3, pp. 337–350, Mar. 1978.
19. C. J. Varker and K. V. Ravi, “Oxidation-induced stacking faults in silicon, II. Electrical effects in p-n diodes,” J. Applied Phys., vol. no. 1, pp. 272-287, Jan. 1974.
20. P. V. Calzolari, S. Graffi, and C. Morandi, “Field-enhanced carrier generation in MOS capacitors,” Solid-State Electron., vol. 17, pp. 1001–1011, 1974.
21. C. Werner, A. Eder, and H. Bernt, “Field enhanced carrier generation in MOS-capacitors containing defects,” Solid-State Electron., vol. 24, pp. 275–279, 1981.
22. G. Vincent, A. Chantre, and D. Bois, “Electric field effect on the thermal emission of traps in semiconductor junctions,” J. Applied Phys., vol. 50, pp. 5484–5487, Aug. 1979.
23. R. Van Overstraeten and H. DeMan, “Measurement of the ionization rates in diffused silicon p-n junctions,” Solid-State Electron., vol. 13, pp. 583–608, 1970.
24. H. F. John, “Silicon power device material problems,” Proc. IEEE, vol. 55, no. 8, pp. 1249–1271, Aug. 1967.
25. R. L. Batdorf, A. G. Chynoweth, G. C. Dacey, and P. W. Fox, “Uniform silicon p-n junction. I. Broad area breakdown,” J. Applied Phys., vol. 31, no. 7, pp. 1153–1160, July 1960.
26. I. Sakata, Y. Hayashi, M. Yamanaka, and M. Satoh, “Carrier separation effects in hydrogenated amorphous silicon photoconductors with multilayer structures,” IEEE Electron Device Lett., vol. EDL-6, pp. 166–168, Apr. 1985.
27. A. Chiang and N. M. Johnson, “High-gain photodetectors in thin-film transistors fabricated from laser-crystallized silicon on fused silica,” in IEDM Tech. Dig., pp. 548–551, 1984.
28. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967, p. 134.