A novel gate-overlapped LDD poly-Si thin-film transistor

IEEE Electron Device Letters

Volumn 17, Issue 12, 1996, Pages 566-568

  Choi, Kwon Young ^a   Han, Min Koo ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FABRICATION; GATES (TRANSISTOR); ION IMPLANTATION; LEAKAGE CURRENTS; OXIDES; POLYCRYSTALLINE MATERIALS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING;

ON CURRENT; ON OFF CURRENT RATIO; POLYSILICON;

THIN FILM TRANSISTORS;

EID: 0030405963     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.545772     Document Type: Article

References (11)

1. J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banerjee, "Anomalous leakage current in LPCVD polysilicon MOSFET's," IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1878-1884, 1985.
2. K. Tanaka, H. Arai, and S. Kohda, "Characteristics of offset-structure polycrystalline-silicon thin-film transistors," IEEE Electron Device Lett., vol. 9, no. 1, pp. 23-25, 1988.
3. S. Seki, O. Kogure, and B. Tsujiyama, "Leakage current characteristic of offset-gate-structure polycrystalline-silicon MOSFET's" IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 434-436, 1987.
4. B. H. Min, C. M. Park, and M. K. Han, "A novel offset gated polysilicon thin-film transistor without an additional offset mask," IEEE Electron Device Lett., vol. 16, no. 5, pp. 161-163, 1995.
5. T. Y. Huang, I.-W. Wu, A. G. Lewis, A. Chiang, and R. H. Bruce, "A simpler 100-V polysilicon TFT with improved turn-on characteristics," IEEE Electron Device Lett., vol. 11, no. 6, pp. 244-246, 1990.
6. T. Y. Huang, J.-W. Wu, A. G. Lewis, A. Chiang, and R. H. Bruce, "Device sensitivity of field-plated polysilicon high-voltage TFT's and their application to low-voltage operation," IEEE Electron Device Lett., vol. 11, no. 11, pp. 541-543, 1990.
7. K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, "Characteristics of field-induced-drain (FID) poly-si TFT's with high ON/OFF current ratio," IEEE Trans. Electron Devices, vol. 39, no. 4, pp. 916-919, 1992.
8. Y. S. Kim, K. Y. Choi, S. K. Lee, B. H. Min, and M. K. Han, "Structural dimension effects of plasma hydrogenation on low-tempenlure poly-si thin-film transistors," Jpn. J. Appl. Phys., vol. 33, pp. 649-653, 1994.
9. K. Y. Choi, and M. K. Han "Two-step annealed polycrystalline silicon thin-film transistors," J. Appl. Phys., vol. 80, no. 3, pp. 1883-1890, 1996.
10. K. Marayam, J. C. Lee, and C. Hu, "A model for the electric field in lightly-doped drain structures," IEEE Trans. Electron Devices, vol. ED-34, no. 7, pp. 1509, 1987.
11. M. Hack, A. Chiang, T. Y. Huang, A. G. Lewis, R. A. Martin, H. Tuan, I. W. Wu, and P. Yap, "High voltage thin-film transistors for large area microelectronics," in IEDM Tech. Dig., 1988, pp. 252-255.