Leakage Current Characteristics of Offset-Gate-Structure Polycrystalline-Silicon MOSFET's

IEEE Electron Device Letters

Volumn 8, Issue 9, 1987, Pages 434-436

  Seki, Shunji ^a   Kogure, Osamu ^a   Tsujiyama, Bunjiro ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTING SILICON;

LEAKAGE CURRENT CHARACTERISTICS; POLYCRYSTALLINE SILICON MOSFET;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0023421569     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1987.26684     Document Type: Article

References (8)

1. S. D. S. Malhi et al., “Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline silicon,” IEEE Trans. Electron Devices, vol, ED-32, p. 258. Feb. 1985.
2. J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banerjee, “Anomalous leakage current in LPCVD polysilicon MOSFET's,” IEEE Trans. Electron Devices, vol. ED-32, p. 1878, Sept. 1985.
3. S. K. Madan and D. A. Antoniadis, “Leakage current mechanisms in hydrogen-passivated fine-grain polycrystalline-silicon on insulator MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, p. 1518, Oct. 1986.
4. H. C. De Graaff, M. Huybers, and J. G. De Groot, “Grain boundary states and the characteristics of lateral polysilicon diodes,” Solid-State Electron., vol. 25, p. 67, Jan. 1982.
5. S. Seki, O. Kogure, and B. Tsujiyama, “Laser-recrystallized polycrystalline-silicon thin-film transistors’ with low leakage current and high switching ratio,” IEEE Electron Device Lett., vol. EDL-8, no. 9. pp. 425–427, Sept. 1987.
6. S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Sheprad, “Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor,” IEEE Trans. Electron Devices, vol. ED-27, p. 1359, 1980.
7. S. Seki, O. Kogure and B. Tsujiyama, “Effects of crystallization on trap state densities at grain boundaries in polycrystalline silicon,” IEEE Electron Device Lett., vol. EDL-8, no. 8, pp. 368–370, Aug. 1987.
8. F. S. Lai, “An analytic model to estimate the avalanche breakdown voltage improvement for LDD devices,” Solid-State Electron., vol. 28, p. 959, Oct. 1985.