CHarge-Based Fault Simulation for CMOS network breaks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1555-1567

  Konuk, Haluk ^a   Joel Ferguson, F ^a   Larrabee, Tracy ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CHARGE; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; NETWORKS (CIRCUITS); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS;

FAULT SIMULATION ALGORITHM; MILLER FEEDBACK CAPACITANCES; MILLER FEEDTHROUGH CAPACITANCES; TRANSISTOR CHARGE MODEL;

CMOS INTEGRATED CIRCUITS;

EID: 0030393452     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552089     Document Type: Article

References (21)

1. Z. Barzilai, J. L. Carter, V. S. lyengar, I. Nair, B. K. Rosen, J. Rutledge, and G. M. Silberman, "Efficient fault simulation of CMOS circuits with accurate models," in Proc. Int. Test Conf., Oct. 1986, pp. 520-529.
2. V. H. Champac, A. Rubio, and J. Figueras, "Electrical model of the floating gate defect in CMOS IC's: Implications on IDDQ testing," IEEE Trans. Computer-Aided Design, pp. 359-369, Mar. 1994.
3. H. Cox and J. Rajski, "Stuck-open and transition fault testing in CMOS complex gates," in Proc. Int. Test Conf., Oct. 1988, pp. 688-694.
4. C. Di and J. A. G. Jess, "On accurate modeling and efficient simulation fo CMOS opens," in Proc. Int. Test Conf., Oct. 1993, pp. 875-882.
5. M. Favalli, M. Dalpasso, P. Olivo, and B. Ricco, "Modeling of broken connections faults in CMOS IC's," in Proc. Europ. Design and Test Conf., 1994.
6. C. F. Hawkins, J. M. Soden, A. W. Righter, and F. J. Ferguson, "Defect classes-An overdue paradigm for CMOS 1C testing," in Proc. Int. Test Conf., Oct. 1994, pp. 413-425.
7. A. Jee and F. J. Ferguson, "Carafe: An inductive fault analysis tool for CMOS VLSI circuits," in Proc. IEEE VLSI Test Symp., 1993.
8. N. K. Jha and J. A. Abraham, "Design of testable CMOS logic circuits under arbitrary delays," IEEE Trans. Computer-Aided Design, pp. 264-269, July 1985.
9. H. Konuk, F. J. Ferguson, and T. Larrabee, "Accurate and efficient fault simulation of realistic CMOS network breaks," in Proc. Design Automation Conf., June 1995, pp. 345-351.
10. T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Trans. Computer-Aided Design, pp. 6-22, Jan. 1992.
11. K.-J. Lee and M. A. Breuer, "On the charge sharing problem in CMOS stuck-open fault testing," in Proc. Int. Test Conf., Oct. 1990, pp. 417-425.
12. W. M. Maly, P. K. Nag, and P. Nigh, "Testing oriented analysis of CMOS IC's with opens," in Proc. Int. Conf. Computer-Aided Design, Nov. 1988, pp. 344-347.
13. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE. New York: McGraw-Hill, 1993.
14. Meta-Software. HSPICE User's Manual: Elements and Models. 1992.
15. S. M. Reddy, M. K. Reddy, and J. G. Kühl, "On testable design for CMOS logic circuits," in Proc. Int. Test Conf., Oct. 1983, pp. 435-445.
16. M. Renovell and G. Cambon, "Electrical analysis and modeling of floating-gate fault," IEEE Trans. Computer-Aided Design, pp. 1450-1458, Nov. 1992.
17. J. Rogenski and F. J. Ferguson, "Characterization of opens in logic circuits," in Proc. IEEE ASIC Conf., 1994.
18. B. J. Sheu, W.-J. Hsu, and P. K. Ko, "An MOS transistor charge model for VLSI design," IEEE Trans. Computer-Aided Design, Apr. 1988, pp. 520-527.
19. B. Underwood, S. Kang, W.-O. Law, and H. Konuk, "Fastpath: Robust path-delay test generator for standard scan designs," in Proc. Int. Test Conf., Oct. 1994, pp. 154-163.
20. J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and Th. McCarthy, "Fault simulation for structured VLSI," in VLSI Syst. Design, Dec. 1985, pp. 20-32.
21. J.-F. Wang, T.-Y. Kuo, and J.-Y. Lee, "A new approach to derive robust tests for stuck-open faults in CMOS combinational logic circuits," in Proc. Design Automation Conf., June 1989, pp. 726-729.