Design of Testable CMOS Logic Circuits Under Arbitrary Delays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 4, Issue 3, 1985, Pages 264-269

  Jha, Niraj K ^a   Abraham, Jacob A ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 3242854837     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1985.1270122     Document Type: Article

References (9)

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4. [4] K. W. Chiang and Z. G. Vranesic, “On fault detection in CMOS logic networks,” in 20th Design Automation Conf., pp. 50–56, June 1983.
5. [5] Y. M. El-Ziq, “Automatic test generation for stuck-open faults in CMOS VLSI,” in 18th Design Automation Conf., Nashville, TN, pp. 347–354, June 1981.
6. [6] Y. M. El-Ziq and R. J. Cloutier, “Functional-level test generation for stuck-open faults in CMOS VLSI,” in 1981 Int. Test Conf., Philadelphia, PA, pp. 536–546, Oct. 1981.
7. [7] S. M. Reddy, M. K. Reddy, and J. G. Kuhl, “On testable design for CMOS logic circuits,” in 1983 Int. Test Conf., Philadelphia, PA, 435–445, 445, Oct. 1983.
8. [8] S. M. Reddy, M. K. Reddy, and V. D. Agrawal, “Robust tests for stuck-open faults in CMOS combinational logic circuits,” Int. Symp. on Fault-Tolerant Computing, Orlando, FL, pp. 44–49, June 1984.
9. [9] R. L. Wadsack, “Fault modelling and logic simulators of CMOS and MOS integrated circuits,” Bell Syst. Tech. J., vol. 57, pp. 1449–1473, May-June 1978.