Accurate and efficient fault simulation of realistic CMOS network breaks

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 345-351

  Konuk, Haluk ^a   Ferguson, F Joel ^a   Larrabee, Tracy ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CHARGE; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; SIMULATORS; TRANSISTORS;

CHARGE SHARING; CMOS NETWORK BREAKS; FAULT SIMULATION; FAULT SIMULATOR; MILLER EFFECT;

CMOS INTEGRATED CIRCUITS;

EID: 0029236385     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217553     Document Type: Conference Paper

References (20)