EFFICIENT FAULT SIMULATION OF CMOS CIRCUITS WITH ACCURATE MODELS.

Digest of Papers - International Test Conference

Volumn , Issue , 1986, Pages 520-529

  Barzilai, Z ^a   Carter, J L ^a   Iyengar, V S ^a   Nair, I ^a   Rosen, B K ^a   Rutledge, J ^a   Silberman, G M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES - GATES; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICES, MOS;

CMOS BOOK SETS; FAULT MODELS;

LOGIC CIRCUITS;

EID: 0022865883     PISSN: 07431686     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)