New approach to derive robust tests for stuck-open faults in CMOS combinational logic circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1989, Pages 726-729

  Wang, Jhing Fa ^a   Kuo, Tah Yuan ^a   Lee, Jau Yien ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICES, MOS;

CMOS COMBINATORIAL CIRCUITS; ROBUST TESTS; ROBUSTNESS VERIFICATION; STUCK-OPEN FAULTS; TWO-PATTERN TEST;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0024908986     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)