Characterization of opens in logic circuits

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1994, Pages 358-361

  Rogenski, Jeffrey S ^a   Ferguson, F Joel ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; PROBABILITY; STATISTICS;

BENCHMARK CIRCUITS; COMBINATIONAL CIRCUIT LAYOUTS; FLOATING NODES CAUSE STUCK AT FAULTS; MULTIPLE STUCK AT FAULTS; REACTILINEAR CIRCUIT LAYOUTS;

LOGIC CIRCUITS;

EID: 0028727911     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)