An MOS Transistor Charge Model for VLSI Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 4, 1988, Pages 520-527

  Sheu, Bing J ^a   Hsu, Wen Jay ^a   Ko, Ping K ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI - COMPUTER AIDED DESIGN; TRANSISTORS;

CARRIER-VELOCITY SATURATION EFFECT; DISTRIBUTED CHARGE DENSITIES; DRAIN AND SOURCE COMPONENTS; MOS TRANSISTOR CHARGE MODEL; PARTITION OF CHANNEL CHARGE;

SEMICONDUCTOR DEVICES, MOS;

EID: 0023998115     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3186     Document Type: Article

References (30)

1. J. E. Meyer, “MOS models and circuit simulation”, RCA Rev., vol. 32, pp. 42-63, Mar. 1971.
2. D. E. Ward, “Charge-based modeling of capacitance in MOS transistor”, Ph.D. dissertation, Tech. Rep. G 201-11, Integrated Circuit Laboratory, Stanford University, June 1981.
3. S.-Y. Oh, D. E. Ward, and R. W. Dutton, “Transient analysis of MOS transistors”, IEEE J. Solid-State Circuits, vol. SC-15, no. 4, pp. 636-643, Aug. 1980.
4. P. Yang, B. D. Epler, and P. K. Chatterjee, “An investigation of the charge conservation problem for MOSFET circuit simulation”, IEEE J. Solid-State Circuits, vol. SC-18, no. 1, pp. 128-138, Feb. 1983.
5. D. E. Ward and R. W. Dutton, “A charged-oriented model for MOS transient capacitances”, IEEE J. Solid-State Circuits, vol. SC-13, no. 4, pp. 703-707; Oct. 1978.
6. Dick Dowell, Hewlett-Packard Company, private communication.
7. L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits”, Univ. California, Berkeley, ERL Memo ERL-M520, May 1975.
8. R. S. C. Cobbold, Theory and Applications of FET's. New York: Wiley-Interscience, 1970, pp. 272-304.
9. C. R. Viswanathan and M. E. Levy, “Modeling inter-electrode capacitances in a MOS transistor”, in Proc. IEEE Int. Electron Devices Meeting, 1979, pp. 38-41.
10. J. A. Robinson, Y. A. El-Mansy, and A. R. Boothroyd, “A general four-terminal charging-current model for the insulated-gate field-effect transistor”, Solid-State Electron., vol. 23, pp. 405-410, 1980.
11. J. I. Arreola, “Equivalent-circuit modeling of the large-signal transient response of four-terminal MOS field transistors”, Ph.D. dissertation, University of Florida, 1978.
12. J. G. Fossum, H. Jeong, and S. Veeraraghavan, “Significance of the channel-charge partition in the transient MOSFET model”, IEEE Trans. Electron Devices, vol. ED-33, pp. 1621-1623, Oct. 1986.
13. R. Conilogue, “A large and small signal charge storage model for an enhancement mode M.O.S. field effect transistor”, Ph.D. dissertation, Dept. Electrical Engineering, University of California, Los Angeles, 1983.
14. J. R. Burns, “Large-signal transit-time effects in the MOS transistors”, RCA Rev., vol. 15, pp. 14-35, Mar. 1969.
15. B. J. Sheu, P. K. Ko, and C. Hu, “On the high-frequency and highspeed characteristics of MOS VLSI circuits”, in IEEE 2nd Symp. VLSI Technol. Syst., Appl. Tech. Dig., (Taipei, Taiwan), May 1985, pp. 231-234.
16. M. E. Zhan, “Calculation of the turn-on behavior of MOST”, Solid-State Electron., vol. 17, pp. 843-854, 1974.
17. M. Bagheri and Y. Tsividis, “A small-signal high-frequency model for the four-terminal intrinsic MOSFET valid in all regions of operation”, in Proc. IEEE Int. Electron Devices Meeting, Dec. 1984, pp. 617-620.
18. J. J. Paulos and D. A. Antoniadis, “Limitations of quasistatic capacitance models for the MOS transistor”, IEEE Electron Device Lett., vol. EDL-4, pp. 221-224, July 1983.
19. C. Turchetti, P. Mancini, and G. Masetti, “A CAD-oriented non-quasi-static approach for the transient analysis of MOS IC's”, IEEE J. Solid-State Circuits, vol. SC-21, no. 5, pp. 827-836, Oct. 1986.
20. B. J. Sheu and C. Hu, “Switched-induced error voltage on a switched capacitor”, IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 519-525, Aug. 1984.
21. J. B. Kuo, R. W. Dutton, and B. A. Wooley, “MOS pass transistor turn-off transient analysis”, IEEE Trans. Electron Devices, vol. ED-33, pp. 1545-1555, Oct. 1986.
22. B. J. Sheu and P. K. Ko, “Short-channel effects on MOS transistor capacitances”, IEEE Trans. Circuits Syst., vol. CAS-33, pp. 1030-1032, Oct. 1986.
23. B. J. Sheu, D. L. Scharfetter, C. Hu, and D. O. Pederson, “A compact IGFET charge model”, Electron. Res. Lab. Memo. ERL-M84/ 20, Univ. of California, Berkeley, Mar. 1984.
24. S. Liu and L. W. Nagel, “Small-signal MOSFET models for analog circuit design”, IEEE J. Solid-Stale Circuits, vol. SC-17, no. 6, pp. 983-998, Dec. 1982.
25. B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M.-C. Jeng, “BSIM: Berkeley short-channel 1GFET model for MOS transistors”, IEEE J. Solid-State Circuits, vol. SC-22, no. 4, Aug. 1987.
26. H. Shichman and D. A. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits”, IEEE J. Solid-State Circuits, vol. SC-3, pp. 285-289, Sept. 1968.
27. Y. Tsividis, “Problems with precision modeling of analog MOS LSI”, in Proc. IEEE Int. Electron Devices Meeting, Dec. 1982, pp. 274-277.
28. B. J. Sheu, P. K. Ko, and F.-C. Hsu, “Characterization of intrinsic capacitances of small-geometry MOSFETs”, IEEE Symp. VLSI TechnoI. Tech. Dig., Sept. 1984, pp. 80-81.
29. R. Shrivastava and K. Fitzpatrick, “A simple model for the overlap capacitance of a VLSI MOS device”, IEEE Trans. Electron Devices, vol. ED-29, pp. 1870-1875, Dec. 1982.
30. B. J. Sheu and P. K. Ko, “An analytical model for intrinsic capacitances of short-channel MOSFETs”, in Proc. IEEE Int. Electron Devices Meeting, Dec. 1984, pp. 300-303.