Electrical Model of the Floating Gate Defect in CMOS ICs: Implications on IDDQ Testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 3, 1994, Pages 359-369

  Champac, Victor H ^a   Rubio, Antonio ^b   Figueras, Joan ^b  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

electrical defect characterization; Floating gate defect model; quiescent current; testing

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DEFECTS; ELECTRIC CHARGE; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRIC NETWORK PARAMETERS; ERROR DETECTION; GATES (TRANSISTOR); MATHEMATICAL MODELS; PARAMETER ESTIMATION;

ELECTRICAL MODELS; FLOATING GATE DEFECTS; QUIESCENT POWER SUPPLY CURRENT; SOFTWARE PACKAGE SPICE; SPOT DEFECTS; STUCK ON TRANSISTOR; STUCK OPEN TRANSISTOR;

CMOS INTEGRATED CIRCUITS;

EID: 0028392267     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.265677     Document Type: Article

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