ON TESTABLE DESIGN FOR CMOS LOGIC CIRCUITS.

Digest of Papers - International Test Conference

Volumn , Issue , 1983, Pages 435-445

  Reddy, Sudhakar M ^a   Reddy, Madhukar K ^a   Kuhl, Jon G ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS LOGIC CIRCUITS; MULTILEVEL CIRCUITS; NAND-NAND NETWORKS; STUCK-OPEN FAULTS; TWO-PATTERN TESTS;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0020887450     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)