Modeling and simulation of broken connections in CMOS IC's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 7, 1996, Pages 808-814

  Favalli, Michele ^a   Dalpasso, Marcello ^b   Olivo, Piero ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITY OF FERRARA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; TRANSISTORS; VECTORS;

BENCHMARK CIRCUIT; STUCK OPEN FAULT;

CMOS INTEGRATED CIRCUITS;

EID: 0030196586     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.503947     Document Type: Article

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