Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

Bell System Technical Journal

Volumn 57, Issue 5, 1978, Pages 1449-1474

  Wadsack, R L ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN;

INTEGRATED CIRCUITS;

EID: 0017961684     PISSN: 00058580     EISSN: 15387305     Source Type: Journal    
DOI: 10.1002/j.1538-7305.1978.tb02106.x     Document Type: Article

References (7)

1. “lamp: Logic Analyzer for Maintenance Planning,”
2. “Development of cos/mos Technology,”
3. “Interactive Logic Simulation and Test Pattern Development for Digital Circuitry,”