Fault Modeling for Digital MOS Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 3, Issue 3, 1984, Pages 200-208

  Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS - FAILURE;

CONNECTOR-SWITCH-ATTENUATOR (CSA) ANALYSIS; FAULT MODELING TECHNIQUE; GENERALIZED SINGLE STUCK-LINE (GSSL) FAULT MODEL;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0021460599     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1984.1270076     Document Type: Article

References (15)

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