메뉴 건너뛰기




Volumn 2, Issue 6, 1985, Pages 13-26

Inductive Fault Analysis of MOS Integrated Circuits

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT-LEVEL FAULT EXTRACTION; CLASSIFICATION AND RANKING OF FAULT TYPES; INDUCTIVE FAULT ANALYSIS (IFA); NONCLASSICAL FAULTS; PHYSICAL DEFECT GENERATION;

EID: 0022201294     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.1985.294793     Document Type: Article
Times cited : (257)

References (15)
  • 1
    • 0019029590 scopus 로고
    • Physical Versus Logical Fault Models in MOS LSI Circuits: Impact on Their Testability
    • June
    • J. Galiay, Y. Crouzet, and M. Vergniault, “Physical Versus Logical Fault Models in MOS LSI Circuits: Impact on Their Testability,” IEEE Trans. Computers, Vol. C-29, No. 6, June 1980, pp. 527–531.
    • (1980) IEEE Trans. Computers , vol.C-29 , Issue.6 , pp. 527-531
    • Galiay, J.1    Crouzet, Y.2    Vergniault, M.3
  • 2
    • 0017961684 scopus 로고
    • Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits
    • May-June
    • R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,” Bell Systems Technical J., May-June 1978, pp. 1449–1474.
    • (1978) Bell Systems Technical J. , pp. 1449
    • Wadsack, R.L.1
  • 4
    • 0020899831 scopus 로고
    • Non-Stuck-At Fault Detection in NMOS Circuits by Region Analysis
    • Philadelphia, Penn., Oct.
    • P. Lamoureux and V.K. Agarwal, “Non-Stuck-At Fault Detection in NMOS Circuits by Region Analysis,” Proc. Int'l Test Conf., Philadelphia, Penn., Oct. 1983, pp. 129–137.
    • (1983) Proc. Int'l Test Conf. , pp. 129-137
    • Lamoureux, P.1    Agarwal, V.K.2
  • 5
    • 0021541891 scopus 로고
    • Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells
    • Philadelphia, Penn., Oct.
    • W. Maly, F.J. Ferguson, and J.P. Shen, “Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells,” Proc. Int'l Test Conf., Philadelphia, Penn., Oct. 1984, pp. 390–399.
    • (1984) Proc. Int'l Test Conf. , pp. 390-399
    • Maly, W.1    Ferguson, F.J.2    Shen, J.P.3
  • 6
    • 0020846899 scopus 로고
    • Modeling of Integrated Circuit Defect Sensitivities
    • November
    • C.H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities,” IBM J. Research and Development, Vol. 27, No. 6, November 1983, pp. 549–557.
    • (1983) IBM J. Research and Development , vol.27 , Issue.6 , pp. 549-557
    • Stapper, C.H.1
  • 7
    • 27644592104 scopus 로고
    • Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
    • July
    • W. Maly, “Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits,” IEEE Trans. Computer-Aided Design, Vol. OE-10, No. 3, July 1985, pp. 166–177.
    • (1985) IEEE Trans. Computer-Aided Design , vol.OE-10 , Issue.3 , pp. 166-177
    • Maly, W.1
  • 9
    • 0021444258 scopus 로고
    • Sources of Failures and Yield Improvement for VLSI and Restructurable Interconnects for RVLSI and WSI: Part I—Sources of Failures and Yield Improvements for VLSI
    • June
    • T.E. Mangir, “Sources of Failures and Yield Improvement for VLSI and Restructurable Interconnects for RVLSI and WSI: Part I—Sources of Failures and Yield Improvements for VLSI,” Proc. of IEEE, June 1984, pp. 690–708.
    • (1984) Proc. of IEEE , pp. 690-708
    • Mangir, T.E.1
  • 10
    • 84944984837 scopus 로고
    • Inductive Fault Analysis of NMOS and CMOS Integrated Circuits
    • ECE Department, CMU, SRC-CAD Center Research Report No. CMUCAD-85-51, Aug.
    • J.P. Shen, W. Maly, and F.J. Ferguson, “Inductive Fault Analysis of NMOS and CMOS Integrated Circuits,” ECE Department, CMU, SRC-CAD Center Research Report No. CMUCAD-85-51, Aug. 1985.
    • (1985)
    • Shen, J.P.1    Maly, W.2    Ferguson, F.J.3
  • 11
    • 0021441367 scopus 로고
    • The Design of Easily Testable VLSI Array Multipliers
    • June
    • J.P. Shen and F.J. Ferguson, “The Design of Easily Testable VLSI Array Multipliers,” IEEE Trans. Computers, Vol. C-33, No. 6, June 1984, pp. 554–560.
    • (1984) IEEE Trans. Computers , vol.C-33 , Issue.6 , pp. 554-560
    • Shen, J.P.1    Ferguson, F.J.2
  • 13
    • 0020091279 scopus 로고
    • Fault Diagnosis of MOS Combinational Networks
    • Feb.
    • Y.M. El-Ziq and S.Y.H. Su, “Fault Diagnosis of MOS Combinational Networks,” IEEE Trans. Computers, Vol. C-31, No. 2, Feb. 1982, pp. 129–139.
    • (1982) IEEE Trans. Computers , vol.C-31 , Issue.2 , pp. 129-139
    • El-Ziq, Y.M.1    Su, S.Y.H.2
  • 14
    • 0022223512 scopus 로고
    • Towards a Switch-Level Test Pattern Generation Program
    • Santa Clara, Calif., Nov.
    • S.H. Robinson and J.P. Shen “Towards a Switch-Level Test Pattern Generation Program,” Proc. Int'l Conf. Computer-Aided Design, Santa Clara, Calif., Nov. 1985.
    • (1985) Proc. Int'l Conf. Computer-Aided Design
    • Robinson, S.H.1    Shen, J.P.2
  • 15
    • 0022188560 scopus 로고
    • VLASIC: A Yield Simulator for Integrated Circuits
    • Santa Clara, Calif., Nov.
    • H. Walker and S.W. Director “VLASIC: A Yield Simulator for Integrated Circuits,” Int'l Conf Computer-Aided Design, Santa Clara, Calif., Nov. 1985.
    • (1985) Int'l Conf Computer-Aided Design
    • Walker, H.1    Director, S.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.