REALISTIC FAULT MODELING FOR VLSI TESTING.

Proceedings - Design Automation Conference

Volumn , Issue , 1987, Pages 173-180

  Maly, Wojciech ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING - COMPUTER APPLICATIONS; LOGIC CIRCUITS - TESTING;

FAULT MODELING; FUNCTIONAL FAILURES; PROCESS-INDUCED DEFECTS;

INTEGRATED CIRCUITS, VLSI;

EID: 0023210701     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/37888.37914     Document Type: Conference Paper

References (26)