An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

IEEE Transactions on Computers

Volumn C-30, Issue 3, 1981, Pages 215-222

  Goel, Prabhakar ^a  

^a IBM   (United States)

Author keywords

Combinational logic; D algorithm; decision tree; error correction; implicit enumeration stuck faults; test generation; untestable fault

Indexed keywords

COMPUTER PROGRAMMING - SUBROUTINES;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0019543877     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1981.1675757     Document Type: Article

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