Electrical-Spin Transduction for CMOS-Spintronic Interface and Long-Range Interconnects

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Volumn 3, Issue , 2017, Pages 47-55

  Mousavi Iraei, Rouhollah ^a   Manipatruni, Sasikanth ^b   Nikonov, Dmitri E ^b   Young, Ian A ^b   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

All spin logic (ASL); CMOS; interconnects; modelling; spintronics; transducers

Indexed keywords

BACTERIOPHAGES; CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; ENERGY DISSIPATION; MODELS; OPTICAL INTERCONNECTS; SPINTRONICS; TRANSDUCERS; TUNNELLING MAGNETORESISTANCE;

AREA OVERHEAD; LONG INTERCONNECT; POWER PRODUCTS; SHORTER DELAYS; SPIN LOGIC; SPIN SIGNAL; SUPPLY VOLTAGES; TUNNEL MAGNETORESISTANCE;

INTEGRATED CIRCUIT INTERCONNECTS;

ELECTRIC CIRCUITS; FUZZY LOGIC; TRANSDUCERS;

EID: 85045095401     PISSN: None     EISSN: 23299231     Source Type: Journal    
DOI: 10.1109/JXCDC.2017.2706671     Document Type: Article

References (41)

1. G. E. Moore, Cramming more components onto integrated circuits,'' Electronics, vol. 38, no. 8, pp. 114-117, Apr. 1965.
2. S. E. Thompson and S. Parthasarathy, Moore's law: The future of Si microelectronics,'' Mater. Today, vol. 9, no. 6, pp. 20-25, 2006.
3. T. N. Theis and P. M. Solomon, It's time to reinvent the transistor,'' Science, vol. 327, no. 5973, pp. 1600-1601, 2010.
4. K. Galatsis et al., Alternate state variables for emerging nanoelectronic devices,'' IEEE Trans. Nanotechnol., vol. 8, no. 1, pp. 66-75, Jan. 2009.
5. G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, Overview of candidate device technologies for storageclass memory,'' IBM J. Res. Develop., vol. 52, nos. 4-5, pp. 449-464, 2008.
6. A. Naeemi, A. Ceyhan, V. Kumar, C. Pan, R. M. Iraei, and S. Rakheja, BEOL scaling limits and next generation technology prospects,'' in Proc. 51st Annu. Design Autom. Conf. Design Autom. Conf., Jun. 2014, pp. 1-6.
7. R. M. Iraei et al., Impact of dimensional scaling and size effects on beyond CMOS all-spin logic interconnects,'' in Proc. Interconnect Technol. Conf./Adv. Metallization Conf., May 2014, pp. 353-356.
8. G. Schmidt, D. Ferrand, L.W. Molenkamp, A. T. Filip, and B. J. vanWees, Fundamental obstacle for electrical spin injection from a ferromagnetic metal into a diffusive semiconductor,'' Phys. Rev. B, Condens. Matter, vol. 62, no. 8, pp. 4790-4793, 2000.
9. S.-C. Chang, R. M. Iraei, S. Manipatruni, D. E. Nikonov, I. A. Young, and A. Naeemi, Design and analysis of copper and aluminum interconnects for all-spin logic,'' IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 2905-2911, Aug. 2014.
10. S.-C. Chang, S. Manipatruni, D. E. Nikonov, I. A. Young, and A. Naeemi, Design and analysis of Si interconnects for all-spin logic,'' IEEE Trans. Magn., vol. 50, no. 9, Sep. 2014, Art. no. 3400513.
11. L. Su et al., Proposal for a graphene-based all-spin logic gate,'' Appl. Phys. Lett., vol. 106, no. 7, pp. 072407.1-072407.5, 2015.
12. S. Rakheja, S.-C. Chang, and A. Naeemi, Impact of dimensional scaling and size effects on spin transport in copper and aluminum interconnects,'' IEEE Trans. Electron Devices, vol. 60, no. 11, pp. 3913-3919, Nov. 2013.
13. J. Fabian and S. Sarma, Spin relaxation of conduction electrons,'' J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 17, no. 4, pp. 1708-1715, 1999.
14. X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory,'' IEEE Trans. Integr. Circuits Syst., vol. 31, no. 7, pp. 994-1007, Jul. 2012.
15. W. Xu, H. Sun, X. Wang, Y. Chen, and T. Zhang, Design of lastlevel on-chip cache using spin-torque transfer RAM (STT RAM),'' IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 3, pp. 483-493, Mar. 2011.
16. F. Ren, H. Park, C.-K. K. Yang, and D. Markovi, Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs,'' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, pp. 2932-2939, Nov. 2013.
17. X. Luo and D. C.-C. Yu, Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory,'' U.S. Patent 7 764 536, Jul. 27, 2010.
18. B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta, Proposal for an all-spin logic device with built-in memory,'' Nature Nanotechnol., vol. 5, no. 4, pp. 266-270, Apr. 2010. [Online]. Available: http://dx.doi.org/10.1038/nnano.2010.31
19. H. Aghasi, R. M. Iraei, A. Naeemi, and E. Afshari, Smart detector cell: A scalable all-spin circuit for low power non-boolean pattern recognition,'' IEEE Trans. Nanotechnol., vol. 15, no. 3, pp. 356-366, May 2016.
20. V. Q. Diep, B. Sutton, B. Behin-Aein, and S. Datta, Spin switches for compact implementation of neuron and synapse,'' Appl. Phys. Lett., vol. 104, no. 22, pp. 222405.1-222405.5, 2014.
21. V. Calayir, D. E. Nikonov, S. Manipatruni, and I. A. Young, Static and clocked spintronic circuit design and simulation with performance analysis relative to CMOS,'' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 2, pp. 393-406, Feb. 2014.
22. S. Manipatruni, D. E. Nikonov, and I. A. Young, Material targets for scaling all-spin logic,'' Phys. Rev. Appl., vol. 5, no. 1, pp. 014002.1-014002.8, 2016.
23. S. Datta, S. Salahuddin, and B. Behin-Aein, Non-volatile spin switch for Boolean and non-Boolean logic,'' Appl. Phys. Lett., vol. 101, no. 25, p. 252411, 2012.
24. P. Bonhomme et al., Circuit simulation of magnetization dynamics and spin transport,'' IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1553-1560, May 2014.
25. L. Su et al., Current-limiting challenges for all-spin logic devices,'' Sci. Rep., vol. 5, Oct. 2015, Art. no. 14905.
26. S. Ikeda et al., Magnetic tunnel junctions for spintronic memories and beyond,'' IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 991-1002, May 2007.
27. S. Ikeda, J. Hayakawa, Y. M. Lee, F. Matsukura, and H. Ohno, Dependence of tunnel magnetoresistance on ferromagnetic electrode materials in MgO-barrier magnetic tunnel junctions,'' J. Magn. Magn. Mater., vol. 310, no. 2, pp. 1937-1939, Mar. 2007.
28. J. Hayakawa, S. Ikeda, F. Matsukura, H. Takahashi, and H. Ohno, Dependence of giant tunnel magnetoresistance of sputtered CoFeB/MgO/CoFeB magnetic tunnel junctions on MgO barrier thickness and annealing temperature,'' Jpn. J. Appl. Phys., vol. 44, no. 4L, pp. 868-871, 2005.
29. W. Rotjanapittayakul, T. Archer, S. Sanvito, and W. Pijitrojana, A -rst principle study of the massive TMR in magnetic tunnel junction using Fe3Al heusler alloy electrodes and MgO barrier,'' Adv. Mater. Res., vol. 1101, pp. 192-197, Apr. 2015.
30. S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki, and K. Ando, Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions,'' Nature Mater., vol. 3, pp. 868-871, Oct. 2004.
31. S. Chung et al., Fully integrated 54 nm STT-RAM with the smallest bit cell dimension for high density memory application,'' IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2010, pp. 12.7.1-12.7.4.
32. Z. Liang and S. S. Sapatnekar, Energy/delay tradeoffs in all-spin logic circuits,'' IEEE J. Explor. Solid-State Computat., vol. 2, pp. 10-19, Dec. 2016.
33. D. E. Nikonov and I. A. Young, Overview of beyond-CMOS devices and a uniform methodology for their benchmarking,'' Proc. IEEE, vol. 101, no. 12, pp. 2498-2533, Dec. 2013.
34. S. Manipatruni, D. E. Nikonov, and I. A. Young, Modeling and design of spintronic integrated circuits,'' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2801-2814, Dec. 2012.
35. J. Z. Sun, Spin-current interaction with a monodomain magnetic body: A model study,'' Phys. Rev. B, Condens. Matter, vol. 62, no. 1, pp. 570-578, 2000.
36. O. Zografos et al., Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10 nm CMOS,'' in Proc. IEEE 15th Int. Conf. Nanotechnol. (IEEE-NANO), Rome, Italy, Jul. 2015, pp. 686-689.
37. J. Xie, P. K. Meher, and Z. H. Mao, High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations,'' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp. 110-119, Jan. 2015.
38. A. Brataas, G. E. W. Bauer, and P. J. Kelly, Non-collinear magnetoelectronics,'' Phys. Rep., vol. 427, no. 4, pp. 157-255, 2006.
39. M. Beleggia, M. De Graef, and Y. T. Millev, The equivalent ellipsoid of a magnetized body,'' J. Phys. D, Appl. Phys., vol. 39, no. 5, pp. 891-899, 2006.
40. E. Barati, M. Cinal, D. M. Edwards, and A. Umerski, Gilbert damping in magnetic layered systems,'' Phys. Rev. B, Condens. Matter, vol. 90, pp. 014420-1-014420-16, Jul. 2014.
41. (2014). Predictive Technology Model. [Online]. Available: http://ptm.asu.edu/