High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 62, Issue 1, 2015, Pages 110-119

  Xie, Jiafeng ^a   Meher, Pramod Kumar ^b   Mao, Zhi Hong ^a  

^a PA 15260   (United States)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

ASIC; Digit serial; Finite field multiplication; FPGA; High throughput; Redundant basis

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ENERGY EFFICIENCY; GRAPH ALGORITHMS; GRAPHIC METHODS; LOGIC SYNTHESIS; PUBLIC KEY CRYPTOGRAPHY; SIGNAL FLOW GRAPHS;

DIGIT-SERIAL; ELLIPTIC CURVE CRYPTOGRAPHY(ECC); FINITE FIELD MULTIPLICATION; FINITE FIELD MULTIPLIERS; HIGH THROUGHPUT; RECURSIVE DECOMPOSITION ALGORITHMS; REDUNDANT BASIS; SIGNAL FLOW GRAPH (SFG);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 85027952598     PISSN: 15498328     EISSN: 15580806     Source Type: Journal    
DOI: 10.1109/TCSI.2014.2349577     Document Type: Article

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