Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS

IEEE-NANO 2015 - 15th International Conference on Nanotechnology

Volumn , Issue , 2015, Pages 686-689

  Zografos, Odysseas ^a,b   Soree, Bart ^a,b   Vaysset, Adrien ^a   Cosemans, Stefan ^a   Amaru, Luca ^c   Gaillardon, Pierre Emmanuel ^c   De Micheli, Giovanni ^c   Lauwereins, Rudy ^a,b   Sayan, Safak ^a,d   Raghavan, Praveen ^a   Radu, Iuliana P ^a   Thean, Aaron ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c EPFL   (Switzerland)

^d INTEL CORPORATION   (United States)

Author keywords

Circuits and Architecture; Simulation; Spin wave devices; Spintronics

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; MAGNETOELECTRONICS; NANOTECHNOLOGY; RECONFIGURABLE HARDWARE; SPIN WAVES;

BENCHMARKING METHODOLOGY; CMOS TECHNOLOGY; DEVICE CIRCUITS; MICROMAGNETIC MODELING; ORDERS OF MAGNITUDE; POWER PRODUCTS; REFERENCE CIRCUITS; SIMULATION;

INTEGRATED CIRCUIT DESIGN;

EID: 84964318222     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2015.7388699     Document Type: Conference Paper

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