Energy/delay tradeoffs in all-spin logic circuits

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Volumn 2, Issue , 2016, Pages 10-19

  Liang, Zhaoxin ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

All spin logic (ASL); optimization; sizing; spintronics

Indexed keywords

DELAY CIRCUITS; LOGIC CIRCUITS; OPTIMIZATION; SPINTRONICS; TIMING CIRCUITS;

BENCHMARK CIRCUIT; ENERGY DEMANDS; OPTIMAL BALANCE; OPTIMAL PERFORMANCE; SIZING; SPIN LOGIC;

COMPUTER CIRCUITS;

ELECTRIC CIRCUITS; FUZZY LOGIC; OPTIMIZATION;

EID: 85062250984     PISSN: None     EISSN: 23299231     Source Type: Journal    
DOI: 10.1109/JXCDC.2016.2541340     Document Type: Article

References (25)

1. B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta, "Proposal for an all-spin logic device with built-in memory, '' Nature Nanotechnol., vol. 5, no. 4, pp. 266-270, 2010.
2. B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, "Switching energy-delay of all spin logic devices, '' Appl. Phys. Lett., vol. 98, no. 12, pp. 123510-1-123510-3, 2011.
3. B. Behin-Aein, A. Sarkar, and S. Datta, "Modeling circuits with spins and magnets for all-spin logic, '' in Proc. Eur. Solid-State Device Res. Conf. (ESSDERC), 2012, pp. 36-40.
4. S. Manipatruni, D. E. Nikonov, and I. A. Young. (2011). "Circuit the-ory for SPICE of spintronic integrated circuits.'' [Online]. Available: http://arxiv.org/abs/1112.2746
5. S. Manipatruni, D. E. Nikonov, and I. A. Young, "Modeling and design of spintronic integrated circuits, '' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2801-2814, Dec. 2012.
6. S. Srinivasan, V. Diep, B. Behin-Aein, A. Sarkar, and S. Datta. (2013)."Modeling multi-magnet networks interacting via spin currents.'' [Online]. Available: http://arxiv.org/abs/1304.0742
7. S. Chang, S. Dutta, S. Manipatruni, D. E. Nikonov, I. A. Young, and A. Naeemi, "Interconnects for all-spin logic using automotion of domain walls, '' IEEE J. Exploratory Solid-State Comput. Devices Circuits, vol. 1, no. 1, pp. 49-57, Dec. 2015.
8. S. Rakheja and A. Naeemi, "Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling, '' in Proc. 12th IEEE Int. Symp. Quality Electron. Design, Mar. 2011, pp. 1-9.
9. C. Augustine, G. Panagopoulos, B. Behin-Aein, S. Srinivasan, A. Sarkar, and K. Roy, "Low-power functionality enhanced computation architec-Ture using spin-based devices, '' in Proc. IEEE/ACM Int. Symp. Nanosc. Archit. (NANOARCH), Jun. 2011, pp. 129-136.
10. S. Rakheja and A. Naeemi, "Interconnect analysis in spin-Torque devices: Performance modeling, sptimal repeater insertion, and circuit-size lim-its, '' in Proc. IEEE 13th Int. Symp. Quality Electron. Design, Mar. 2012, pp. 283-290.
11. S. Takahashi and S. Maekawa, "Spin current in metals and superconduc-Tors, J. Phys. Soc. Jpn., vol. 77, no. 3, pp. 031009-1-031009-14, 2008.
12. J. C. Slonczewski, "Current-driven excitation of magnetic multilayers, J. Magn. Magn. Mater., vol. 159, nos. 1-2, pp. L1-L7, 1996.
13. D. E. Nikonov, G. I. Bourianoff, G. Rowlands, and I. N. Krivorotov, "Strategies and tolerances of spin transfer torque switching, '' J. Appl. Phys., vol. 107, no. 11, p. 113910, 2010.
14. A. Aharoni, "Demagnetizing factors for rectangular ferromagnetic prisms, '' J. Appl. Phys., vol. 83, no. 6, pp. 3432-3434, 1998.
15. J. G. Ecker, "Geometric programming: Methods, computations and appli-cations, '' SIAM Rev., vol. 22, no. 3, pp. 338-362, 1980.
16. A. Mutapcic, K. Koh, S. Kim, L. Vandenberghe, and S. Boyd. (2006). GGPLAB: A Simple MATLAB Toolbox for Geometric Programming. [Online]. Available: https://stanford.edu/ boyd/ggplab/ggplab.pdf
17. J. P. Fishburn and A. E. Dunlop, "TILOS: A polynomial programming approach to transistor sizing, '' in Proc. IEEE Int. Conf. Comput.-Aided Design, Nov. 1985, pp. 326-328.
18. S. R. Nassif, "Power grid analysis benchmarks, '' in Proc. Asia-South Pacific Design Autom. Conf., 2008. [Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4483978
19. J. E. Stine, et al., "FreePDK: An open-source variation-Aware design kit, '' in Proc. IEEE Int. Conf. Microelec-Tron. Syst. Edu., 2007, pp. 173-174. [Online]. Available: http://ieeexplore.ieee.org/xpls/absfiall.jsp?arnumber=4231502
20. T. Kimura, T. Sato, andY. Otani, "Temperature evolution of spin relaxation in a NiFe/Cu lateral spin valve, '' Phys. Rev. Lett., vol. 100, no. 6, p. 066602, 2008.
21. J. Bass and W. P. Pratt, Jr., "Spin-diffusion lengths in metals and alloys, and spin-fiipping at metal/metal interfaces: An experimentalist's critical review, '' J. Phys., Condens. Matter, vol. 19, no. 18, p. 183201, 2007.
22. S. Rakheja, S.-C. Chang, and A. Naeemi, "Impact of dimensional scal-ing and size effects on spin transport in copper and aluminum intercon-nects, '' IEEE Trans. Electron Devices, vol. 60, no. 11, pp. 3913-3919, Nov. 2013.
23. M. Erekhinsky, A. Sharoni, F. Casanova, and I. K. Schuller, "Surface enhanced spin-fiip scattering in lateral spin valves, '' Appl. Phys. Lett., vol. 96, no. 2, p. 022513, 2010.
24. J. A. Roy, et al., "Capo: Robust and scalable open-source min-cut fioor-placer, '' in Proc. Int. Symp. Phys. Design, 2005, pp. 224-226.
25. L. O. Chua and P.-M. Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques. Englewood Cliffs, NJ, USA: Prentice-Hall, 1975.