메뉴 건너뛰기




Volumn 11, Issue 2, 2017, Pages 813-822

Energy-Aware Data Allocation with Hybrid Memory for Mobile Cloud Systems

Author keywords

Chip multiprocessor (CMP); data allocation; hybrid memory; magnetic RAM (MRAM); mobile cloud; scratchpad memory (SPM); zero capacitor RAM (Z RAM)

Indexed keywords

CACHE MEMORY; DYNAMIC PROGRAMMING; ENERGY UTILIZATION; GREEN COMPUTING; MAGNETIC RECORDING; MAGNETIC STORAGE; MEMORY ARCHITECTURE; MOBILE CLOUD COMPUTING; MRAM DEVICES; MULTIPROCESSING SYSTEMS; POWER MANAGEMENT; REAL TIME SYSTEMS; STATIC RANDOM ACCESS STORAGE;

EID: 85027462438     PISSN: 19328184     EISSN: 19379234     Source Type: Journal    
DOI: 10.1109/JSYST.2014.2345733     Document Type: Article
Times cited : (94)

References (25)
  • 1
    • 0030673565 scopus 로고    scopus 로고
    • A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
    • J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor, " Digital Tech. J., vol. 9, no. 1, pp. 49-62, 1997.
    • (1997) Digital Tech. J , vol.9 , Issue.1 , pp. 49-62
    • Montanaro, J.1
  • 3
    • 0030686025 scopus 로고    scopus 로고
    • Efficient utilization of scratchpad memory in embedded processor applications
    • Mar
    • P. R. Panda, N. D. Dutt, and A. Nicolau, "Efficient utilization of scratchpad memory in embedded processor applications, " in Proc. Eur. Conf. Design Test, Mar. 1997, pp. 7-11.
    • (1997) Proc. Eur. Conf. Design Test , pp. 7-11
    • Panda, P.R.1    Dutt, N.D.2    Nicolau, A.3
  • 4
    • 35648995967 scopus 로고    scopus 로고
    • Introduction to the cell broadband engine architecture
    • Sep
    • C. R. Johns and D. A. Brokenshire, "Introduction to the cell broadband engine architecture, " IBM J. Res. Develop., vol. 51, no. 5, pp. 503-519, Sep. 2007.
    • (2007) IBM J. Res. Develop , vol.51 , Issue.5 , pp. 503-519
    • Johns, C.R.1    Brokenshire, D.A.2
  • 5
    • 77954994037 scopus 로고    scopus 로고
    • Resistive computation: Avoiding the power wall with low-leakage, STT-MRAM based computing
    • X. Guo, E. Ipek, and T. Soyata, "Resistive computation: Avoiding the power wall with low-leakage, STT-MRAM based computing, " in Proc. 37th Annu. ISCA, 2010, pp. 371-382.
    • (2010) Proc. 37th Annu. ISCA , pp. 371-382
    • Guo, X.1    Ipek, E.2    Soyata, T.3
  • 6
    • 76349088483 scopus 로고    scopus 로고
    • Energy reduction for STTRAM using early write termination
    • P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "Energy reduction for STTRAM using early write termination, " in Proc. IEEE/ACM ICCAD, 2009, pp. 264-268.
    • (2009) Proc. IEEE/ACM ICCAD , pp. 264-268
    • Zhou, P.1    Zhao, B.2    Yang, J.3    Zhang, Y.4
  • 7
    • 33847743417 scopus 로고    scopus 로고
    • A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM
    • M. Hosomi et al., "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM, " in Int. Electron Devices Meet., 2005, pp. 459-462.
    • (2005) Int. Electron Devices Meet , pp. 459-462
    • Hosomi, M.1
  • 8
    • 57149128202 scopus 로고    scopus 로고
    • Magnetoresistive random accessmemory: The path to competitiveness and scalability
    • J. G. Zhu, "Magnetoresistive random accessmemory: The path to competitiveness and scalability, " Proc. IEEE, pp. 1786-1798, 2008.
    • (2008) Proc. IEEE , pp. 1786-1798
    • Zhu, J.G.1
  • 9
    • 64949106457 scopus 로고    scopus 로고
    • A novel architecture of the 3D stacked MRAM l2 cache for CMPs
    • G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, "A novel architecture of the 3D stacked MRAM l2 cache for CMPs, " in Proc. 36th Annu. ISCA, 2009, pp. 239-249.
    • (2009) Proc. 36th Annu. ISCA , pp. 239-249
    • Sun, G.1    Dong, X.2    Xie, Y.3    Li, J.4    Chen, Y.5
  • 10
    • 70450243083 scopus 로고    scopus 로고
    • Hybrid cache architecture with disparate memory technologies
    • Jun
    • X. Wu et al., "Hybrid cache architecture with disparate memory technologies, " SIGARCH Comput. Archit. News, vol. 37, no. 3, pp. 34-35, Jun. 2009.
    • (2009) SIGARCH Comput. Archit. News , vol.37 , Issue.3 , pp. 34-35
    • Wu, X.1
  • 11
    • 84872094294 scopus 로고    scopus 로고
    • An optimal memory allocation scheme for scratch-pad based embedded systems
    • Nov
    • O. Avissar, R. Barua, and D. Stewart, "An optimal memory allocation scheme for scratch-pad based embedded systems, " ACM TECS, vol. 1, no. 1, pp. 6-26, Nov. 2002.
    • (2002) ACM TECS , vol.1 , Issue.1 , pp. 6-26
    • Avissar, O.1    Barua, R.2    Stewart, D.3
  • 12
    • 18844371462 scopus 로고    scopus 로고
    • Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
    • Oct
    • S. Udayakumaran and R. Barua, "Compiler-decided dynamic memory allocation for scratch-pad based embedded systems, " in Proc. Int. Conf. CASES, Oct. 2003, pp. 276-286.
    • (2003) Proc. Int. Conf. CASES , pp. 276-286
    • Udayakumaran, S.1    Barua, R.2
  • 13
    • 0034848113 scopus 로고    scopus 로고
    • Dynamic management of scratch-pad memory space
    • Jun
    • M. Kandemir et al., "Dynamic management of scratch-pad memory space, " in Proc. DAC, Jun. 2001, pp. 690-695.
    • (2001) Proc. DAC , pp. 690-695
    • Kandemir, M.1
  • 14
    • 79957545701 scopus 로고    scopus 로고
    • Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory
    • J. Hu, C. J. Xue, Q. Zhuge, W.-C. Tseng, and E. H.-M. Sha, "Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory, " in Proc. Conf. & Exhib. DATE, 2011, pp. 1-6.
    • (2011) Proc. Conf. & Exhib. DATE , pp. 1-6
    • Hu, J.1    Xue, C.J.2    Zhuge, Q.3    Tseng, W.-C.4    Sha, E.H.-M.5
  • 15
    • 65849231067 scopus 로고    scopus 로고
    • Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
    • Mar
    • M. Qiu and E. H.-M. Sha, "Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems, " ACM TODAES, vol. 14, no. 2, pp. 1-30, Mar. 2009.
    • (2009) ACM TODAES , vol.14 , Issue.2 , pp. 1-30
    • Qiu, M.1    Sha, E.H.-M.2
  • 16
    • 84862806683 scopus 로고    scopus 로고
    • Online optimization for scheduling preemptable tasks on IAAS cloud systems
    • May 2012
    • J. Li et al., "Online optimization for scheduling preemptable tasks on IAAS cloud systems, " JPDC, vol. 72, no. 5, pp. 666-677, May 2012.
    • JPDC , vol.72 , Issue.5 , pp. 666-677
    • Li, J.1
  • 17
    • 80052533056 scopus 로고    scopus 로고
    • Architecting on-chip interconnects for stacked 3d STTRAM caches in CMPS
    • A. Mishra et al., "Architecting on-chip interconnects for stacked 3d STTRAM caches in CMPS, " in Proc. 38th Annu. ISCA, 2011, pp. 69-80.
    • (2011) Proc. 38th Annu. ISCA , pp. 69-80
    • Mishra, A.1
  • 18
    • 80052066953 scopus 로고    scopus 로고
    • Exploiting heterogeneity for energy efficiency in chip multiprocessors
    • Jun
    • V. Saripalli et al., "Exploiting heterogeneity for energy efficiency in chip multiprocessors, " IEEE J. Emerging Sel. Topics Circuits Syst., vol. 2, no. 1, pp. 109-119, Jun. 2011.
    • (2011) IEEE J. Emerging Sel. Topics Circuits Syst , vol.2 , Issue.1 , pp. 109-119
    • Saripalli, V.1
  • 19
    • 47649086892 scopus 로고    scopus 로고
    • Dynamic allocation for scratch-pad memory using compile-time decisions
    • May
    • S. Udayakumaran, A. Dominguez, and R. Barua, "Dynamic allocation for scratch-pad memory using compile-time decisions, " ACM TECS, vol. 5, no. 2, pp. 472-511, May 2006.
    • (2006) ACM TECS , vol.5 , Issue.2 , pp. 472-511
    • Udayakumaran, S.1    Dominguez, A.2    Barua, R.3
  • 20
    • 27644567646 scopus 로고    scopus 로고
    • Power efficient processor architecture and the cell processor
    • H. P. Hofstee, "Power efficient processor architecture and the cell processor, " in Proc. IEEE 11th Int. Symp. HPCA, 2005, pp. 258-262.
    • (2005) Proc. IEEE 11th Int. Symp. HPCA , pp. 258-262
    • Hofstee, H.P.1
  • 21
    • 77952031363 scopus 로고    scopus 로고
    • A Hardware/Software Framework for Instruction and Data Scratchpad Memory Allocation, " J
    • Apr
    • Z. H. Chen and A. W. Y. Su, "A Hardware/Software Framework for Instruction and Data Scratchpad Memory Allocation, " J. ACM TACO, vol. 7, no. 1, pp. 2-1-2-27, Apr. 2010.
    • (2010) ACM TACO , vol.7 , Issue.1 , pp. 21-227
    • Chen, Z.H.1    Su, A.W.Y.2
  • 22
    • 80155187624 scopus 로고    scopus 로고
    • Optimal data allocation for scratch-pad memory on embedded multi-core systems
    • Sep
    • Y. Guo, Q. Zhuge, J. Hu, M. Qiu, and E. H.-M. Sha, "Optimal data allocation for scratch-pad memory on embedded multi-core systems, " in Proc. 40th IICPP, Sep. 2011, pp. 464-471.
    • (2011) Proc. 40th IICPP , pp. 464-471
    • Guo, Y.1    Zhuge, Q.2    Hu, J.3    Qiu, M.4    Sha, E.H.-M.5
  • 23
    • 85027440112 scopus 로고    scopus 로고
    • Parsec. [Online]. Available: http://parsec.cs.princeton.edu/
  • 24
    • 33846535493 scopus 로고    scopus 로고
    • The M5 simulator: Modeling networked systems
    • Jul./Aug
    • N. L. Binkert et al., "The M5 simulator: Modeling networked systems, " IEEE Micro, vol. 26, no. 4, pp. 52-60, Jul./Aug. 2006.
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 52-60
    • Binkert, N.L.1
  • 25
    • 47349084021 scopus 로고    scopus 로고
    • Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0
    • Dec
    • N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0, " in Proc. 40th Annu. IEEE/ACM Int. Symp., Dec. 2007, pp. 3-14.
    • (2007) Proc. 40th Annu. IEEE/ACM Int. Symp , pp. 3-14
    • Muralimanohar, N.1    Balasubramonian, R.2    Jouppi, N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.