Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems

ACM Transactions on Design Automation of Electronic Systems

Volumn 14, Issue 2, 2009, Pages

  Qiu, Meikang ^a,c   Sha, Edwin H M ^b,d  

^a UNIVERSITY OF NEW ORLEANS   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

^c UNO College of Engineering   (United States)

^d The University of Texas at Dallas   (United States)

Author keywords

Embedded Systems; Heterogeneous; High level synthesis; Real time

Indexed keywords

CONFIDENCE PROBABILITY; COST MINIMIZATION; EXECUTION TIME; HARD REAL-TIME; HETEROGENEOUS; HETEROGENEOUS EMBEDDED SYSTEM; HETEROGENEOUS FUNCTIONAL UNIT; HIGH-LEVEL SYNTHESIS; OPTIMAL ALGORITHM; OPTIMAL SOLUTIONS; OTHER ALGORITHMS; REAL-TIME; REAL-TIME EMBEDDED SYSTEMS; SOFT REAL-TIME SYSTEMS; TIMING CONSTRAINTS; TOTAL COSTS; WORST CASE SCENARIO;

COSTS; EMBEDDED SYSTEMS; HAZARDOUS MATERIALS; HEURISTIC ALGORITHMS; OPTIMIZATION; RANDOM VARIABLES; TIME MEASUREMENT; TIMING CIRCUITS;

REAL TIME SYSTEMS;

EID: 65849231067     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1497561.1497568     Document Type: Article

References (40)

1. BANINO, C., BEAUMONT, O., CARTER, L., FERRANTE, J., LEGRAND, A., AND ROBERT, Y. 2004. Scheduling strategies for master-slave tasking on heterogeneous processor platforms. IEEE Trans. Parall. Distrib. Syst. 15, 4, 319-330.
2. BEAUMONT, O., LEGRAND, A., MARCHAL, L., AND ROBERT, Y. 2004. Pipelining broadcasts on heterogeneous platforms. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2004), IEEE.
3. BEAUMONT, O., LEGRAND, A., MARCHAL, L., AND ROBERT, Y. 2003a. Scheduling strategies for mixed data and task parallelism on heterogeneous clusters. Parall. Process. Lett. 13, 2, 225-244.
4. BEAUMONT, O., LEGRAND, A., AND ROBERT, Y. 2003b. The master-slave paradigm with heterogeneous processors. IEEE Trans. Parall. Distrib. Syst. 14, 9, 897-908.
5. BEAUMONT, O., LEGRAND, A., AND ROBERT, Y. 2002. Static scheduling strategies for heterogeneous systems. Comput. Informatics 21, 413-430.
6. BETTATI, R. AND LIU, J. W.-S. 1992. End-to-end scheduling to meet deadlines in distributed systems. In Proceedings of the International Conference. on Distributed Computing Systems. 452-459.
7. CHANG, Y.-N., WANG, C.-Y., AND PARHI, K. K. 1996. Loop-list scheduling for heterogeneous functional units. In Proceedings of the 6th Great Lakes Symposium on Very Large-Scale Integration. 2-7.
8. CHAO, L.-F. AND SHA, E. H. -M. 1997. Scheduling dataflow graphs via retiming and unfolding. IEEE Trans. Parall. Distrib. Syst. 8, 1259-1267. (Pubitemid 127767771)
9. CHAO, L. -F. AND SHA, E. H. -M. 1995. Static scheduling for synthesis of dsp algorithms on various models. J.VLSI Signal Process. Syst. 10, 207-223.
10. DE MAN, H., CATTHOOR, F., GOOSSENS, G., VANHOOF, J., VAN MEERBERGEN, S. N., AND HUISKEN, J. A. 1990. Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms. Proc. IEEE 78, 2, 319-335. (Pubitemid 20702277)
11. DOGAN, A. AND ÖZGÜNER, F. 2002. Matching and scheduling algorithms for minimizing execution time and failure probability of applications in heterogeneous computing. IEEE Trans. Parall. Distrib. Syst. 13, 308-323. (Pubitemid 34448783)
12. FOSTER, I. 1994. Designing and Building Parallel Program: Concepts and Tools for Parallel Software Engineering. Addison-Wesley.
13. GEBOTYS, C. H. AND ELMASRY, M. 1993. Global optimization approach for architectural synthesis. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 12, 1266-1278.
14. HE, Y., SHAO, Z., XIAO, B., ZHUGE, Q., AND SHA, E. H. -M. 2003. Reliability driven task schedulingfor tightly coupled heterogeneous systems. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems.
15. Hou, C. -J. AND SHIN, K. G. 1997. Allocation of periodic task modules with precedence and deadline constraints in distributed real-time systems. IEEE Trans. Computers46, 1338-1356. (Pubitemid 127760653)
16. HUA, S. AND Qu, G. 2003. Approaching the maximum energy saving on embedded systems with multiple voltages. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 26-29.
17. HUA, S., QU, G., AND BHATTACHARYYA, S. S. 2003a. Energy reduction techniques for multimedia applications with tolerance to deadline misses. In Proceedings of the Design Automation Conference (DAC'03). 131-136.
18. HUA, S., QU, G., AND BHATTACHARYYA, S. S. 2003b. Exploring the probabilistic design space of multimedia systems. In Proceedings of the IEEE International Workshop on Rapid System Prototyping. 233-240.
19. HWANG, C. -T., LEE, J. -H., AND HSU, Y. -C. 1991. A formal approach to the scheduling problem in high level synthesis. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 10, 464-475.
20. ITO, K., LUCKE, L., AND PARHI, K. 1998. ILP-based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. VLSI Syst. 6, 582-594. (Pubitemid 128745522)
21. ITO, K. AND PARHI, K. 1995. Register minimization in cost-optimal synthesis of dsp architecture. In Proceedings of the IEEE VLSI Signal Processing Workshop.
22. KALAVADE, A. AND MOGHE, P. 1998. A tool for performance estimation of networked embedded end-systems. In Proceedings of the IEEE/ACM Design Automation Conference. 257-262.
23. PARHI, K. AND MESSERSCHMITT, D. G. 1991. Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding. IEEE Trans. Computers 40, 178-195.
24. LESTER, B. P. 1993. The Art of Parallel Programming. Prentice Hall, Englewood Cliffs, NJ.
25. Li, W. N., LIM, A., AGARWAL, P., AND SAHNI, S. 1993. On the circuit implementation problem. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 12, 1147-1156. (Pubitemid 23610470)
26. MCFARLAND, M. C., PARKER, A. C., AND CAMPOSANO, R. 1990. The high-level synthesis of digital systems. Proc. IEEE 78, 301-318. (Pubitemid 20702276)
27. PASSOS, N. L., SHA, E. H. -M., AND BASS, S. C. 1994. Loop pipelining for scheduling multi- dimensional systems via rotation. In Proceedings of the 31st Design Automation Conference.485-490.
28. PAULIN, P. G. AND KNIGHT, J. P. 1989. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 8, 661-679.
29. RAMAMRITHAM, K., STANKOVIC, J. A., AND SHIAH, P. -F. 1990. Efficient scheduling algorithms for real-time multiprocessor systems. IEEE Trans. Parall. Distrib. Syst. 1, 184-194. (Pubitemid 20702078)
30. SHAO, Z., ZHUGE, Q., XUE, C., AND SHA, E. H. -M. 2005. Efficient assignment and scheduling for heterogeneous dsp systems. IEEE Trans. Parall. Distrib. Syst. 16, 516-525.
31. SHATZ, S. M., WANG, J. -P., AND GOTO, M. 1992. Task allocation for maximizing reliability of distributed computer systems. IEEE Trans. Computers 41, 1156-1168. (Pubitemid 23573771)
32. SRINIVASAN, S. AND JHA, N. K. 1999. Safety and reliability driven task allocation in distributed systems. IEEE Trans. Parall. Distrib. Syst. 10, 238-251.
33. TIA, T., DENG, Z., SHANKAR, M., STORCH, M., SUN, J., Wu, L.-C., AND LIU, J. -S. 1995. Prob- abilistic performance guarantee for real-time tasks with varying computation times. In Proceedings of the IEEE Real-Time Technology and Applications Symposium. 164-173.
34. TONGSIMA, S., SHA, E. H. -M., CHANTRAPORNCHAI, C., SURMA, D., AND PASSOSE, N. 2000. Probabilistic loop scheduling for applications with uncertain execution time. IEEE Trans. Computers 49, 65-80. (Pubitemid 30568824)
35. VAHID, F. AND GIVARGIS, T. 2002. Embedded System Design, A Unified Hardware/Software Introduction. Wiley, New York.
36. WANG, C. -Y. AND PARHI, K. K. 1995. High-level synthesis using concurrent transformations, scheduling, and allocation. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 14, 274-295.
37. WOLF, W. 2006. Design challenges in multiprocessor Systems-On-Chip. In From Model-Driven Design to Resource Management for Distributed Embedded Systems, B. Kleinjohann et al. Eds., vol. 225, Springer, 1-8.
38. WOLFE, M. E. 1996. High Performance Compilers for Parallel Computing. Addison-Wesley.
39. ZADEH, L. A. 1996. Fuzzy sets as a basis for a theory of possibility. Fuzzy Sets Syst. 1, 3-28.
40. ZHOU, T., HU, X., AND SHA, E. H. -M. 2001. Estimating probabilistic timing performance for realtime embedded systems. IEEE Trans. VLSI Syst. 9, 6, 833-844. (Pubitemid 34126215)