Dynamic Control for Mixed-Critical Networks-on-Chip

Proceedings - Real-Time Systems Symposium

Volumn 2016-January, Issue , 2016, Pages 317-326

  Kostrzewa, Adam ^a   Saidi, Selma ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

mixed critical; overlay network; real time; safety

Indexed keywords

ACCIDENT PREVENTION; BENCHMARKING; CRITICALITY (NUCLEAR FISSION); DYNAMICS; INTERACTIVE COMPUTER SYSTEMS; NETWORK-ON-CHIP; OVERLAY NETWORKS;

CRITICAL NETWORKS; DEDICATED PROTOCOLS; HARDWARE OVERHEADS; MIXED CRITICALITIES; MIXED-CRITICAL; NETWORKS ON CHIPS; REAL TIME; SERVICE GUARANTEES;

REAL TIME SYSTEMS;

EID: 84964570364     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2015.37     Document Type: Conference Paper

References (29)

1. L. Benini and G. De Micheli, "Networks on chips: A new soc paradigm," Computer, vol. 35, pp. 70-78, Jan. 2002.
2. "Do-178b-software considerations in airborne systems and equipment certification," Dec. 2009.
3. H. Zhang, "Service disciplines for guaranteed performance service in packet-switching networks," IEEE, 1995.
4. K. Goossens and A. Hansson, "The aethereal network on chip after ten years: Goals, evolution, lessons, and future," in DAC, pp. 306-311, June 2010.
5. R. Pellizzoni, P. Meredith, M.-Y. Nam, M. Sun, M. Caccamo, and L. Sha, "Handling mixed-criticality in soc-based real-time embedded systems," in EMSOFT, ACM, 2009.
6. H. M. G. Wassel, Y. Gao, J. K. Oberg, T. Huffmire, R. Kastner, F. T. Chong, and T. Sherwood, "Surfnoc: A low latency and provably noninterfering approach to secure networks-on-chip," in ISCA, 2013.
7. A. Psarras, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, "Phasenoc: Tdm scheduling at the virtual-channel level for efficient network traffic isolation," in DATE, 2015.
8. A. Hansson, M. Coenen, and K. Goossens, "Channel trees: Reducing latency by sharing time slots in time-multiplexed networks on chip," in CODES+ISSS, pp. 149-154, Sept 2007.
9. Z. P. Wu, Y. Krish, and R. Pellizzoni, "Worst case analysis of dram latency in multi-requestor systems," in RTSS, Dec 2013.
10. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.
11. E. Bolotin and et al., "Qnoc: Qos architecture and design process for network on chip," JOURNAL OF SYSTEMS ARCHITECTURE, 2004.
12. Z. Shi and A. Burns, "Real-time communication analysis for on-chip networks with wormhole switching," in NoCS 2008, 2008.
13. T. Bjerregaard and J. Sparso, "A router architecture for connectionoriented service guarantees in the mango clockless network-on-chip," in DATE, pp. 1226-1231 Vol. 2, March 2005.
14. A. Burns, J. Harbin, and L. Indrusiak, "A wormhole noc protocol for mixed criticality systems," in Real-Time Systems Symposium (RTSS), 2014 IEEE, pp. 184-195, Dec 2014.
15. G. Durrieu, M. Faugere, S. Girbal, D. Gracia Perez, C. Pagetti, and W. Puffitsch, "Predictable flight management system implementation on a multicore processor," in ERTS, 2014.
16. I. Walter, I. Cidon, R. Ginosar, and A. Kolodny, "Access regulation to hot-modules in wormhole nocs," in NOCS, pp. 137-148, May 2007.
17. A. Kostrzewa, S. Tobuschat, P. Axer, and R. Ernst, "Supervised sharing of virtual channels in networks-on-chip," in SIES, 2014.
18. D. Bertozzi, "Noc synthesis flow for customized domain specific multiprocessor systems-on-chip," Parallel and Distributed Systems, vol. 16, pp. 113-129, Feb 2005.
19. A. Schranzhofer, J.-J. Chen, and L. Thiele, "Timing analysis for tdma arbitration in resource sharing systems," in RTAS, pp. 215-224, April 2010.
20. R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley, "A predictable execution model for cots-based embedded systems," in RTAS, 2011.
21. L. Thiele, S. Chakraborty, and M. Naedele, "Real-time calculus for scheduling hard real-time systems," in ISCAS, vol. 4, pp. 101-104 vol.4, 2000.
22. R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst, "System level performance analysis-the symta/s approach," in IEE Proceedings Computers and Digital Techniques, 2005.
23. J. Diemer, P. Axer, and R. Ernst, "Compositional performance analysis in python with pycpa," in WATERS, jul 2012.
24. E. A. Rambo and R. Ernst, "Worst-case communication time analysis of networks-on-chip with shared virtual channels," in DATE, 2015.
25. S. Schliecker and et al, "Providing accurate event models for the analysis of heterogeneous multiprocessor systems," in CODES+ISSS, pp. 185-190, ACM, 2008.
26. K. Richter, Compositional Scheduling Analysis Using Standard Event Models. PhD thesis, TU Braunschweig, IDA, 2005.
27. Y. Ben-Itzhak, E. Zahavi, I. Cidon, and A. Kolodny, "Hnocs: Modular open-source simulator for heterogeneous nocs," in SAMOS, pp. 51-57, July 2012.
28. Y. H. et al., "Proposal and quantitative analysis of the chstone benchmark program suite for practical c-based high-level synthesis," Journal of Information Processing, vol. 17, pp. 242-254, 2009.
29. N. Binkert and et al., "The gem5 simulator," SIGARCH Comput. Archit. News, vol. 39, pp. 1-7, Aug. 2011.