Channel trees: Reducing latency by sharing time slots in time-multiplexed networks on chip

CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2007, Pages 149-154

  Hansson, Andreas ^a   Coenen, Martijn ^b   Goossens, Kees ^b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Network on chip; Quality of service; System on chip; Time division multiplexing

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); QUALITY OF SERVICE; TELECOMMUNICATION SYSTEMS; TIME DIVISION MULTIPLEXING; TREES (MATHEMATICS);

AVERAGE CASE LATENCY; CHANNEL TREES; WORK CONSERVING ARBITRATION;

MICROPROCESSOR CHIPS;

EID: 38849162741     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289816.1289855     Document Type: Conference Paper

References (21)

1. E. Beigne et al. An asynchronous NOC architecture providing low latency service and its multi-level design framework. In Proc. ASYNC, pages 54-63, 2005.
2. M. Bekooij et al. Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications. In Proc. SCOPES, 2007.
3. T. Bjerregaard and J. Sparsø. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In Proc. DATE, 2005.
4. M. Coenen et al. A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. In Proc. CODES+ISSS, 2006.
5. W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. DAC, 2001.
6. S. Dutta et al. Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers, 2001.
7. O. P. Gangwal. Id 693979 - network-on-chip environment and method for reduction of latency. Technical report, Royal Philips Electronics, 2005.
8. K. Goossens et al. A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In Proc. DATE, 2005.
9. R. Guérin and A. Orda. Networks with advance reservations: The routing perspective. In Proc. INFOCOM, 2000.
10. A. Hansson et al. A unified approach to constrained mapping and routing on network-on-chip architectures. In Proc. CODES+ISSS, 2005.
11. JEDEC Solid State Technology Association. DDR2. SDRAM Specification, JESD79-2C edition, 2006.
12. H. Kopetz. Real-Time Systems: Design Principles for Distibuted Embedded Applications. Kluwer Academic Publishers, 1997.
13. A. Laffely. An interconnect-centric approach for adapting voltage and frequency in heterogeneous system-on-a-chip. PhD thesis, University of Massachusetts Amherst, 2003.
14. M. Millberg et al. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In Proc. DATE, 2004.
15. A. Moonen et al. A multi-core architecture for in-car digital entertainment. In Proc. GSPx, 2005.
16. A. Rǎdulescu et al. An efficient on-chip network interface offering guaranteed services, shaxed-memory abstraction, and flexible network programming. IEEE Trans. on CAD of Int. Circ. and Syst., 2005.
17. D. Saha et al. Multi-rate traffic shaping and end-to-end performance guarantees in ATM networks. In Proc. ICNP, 1994.
18. D. Shoemaker. An Optimized Hardware Architecture and Communication Protocol for Scheduled Communication. PhD thesis, Massachusetts Institute of Technology, 1997.
19. S. Stuijk et al. Resource-efficient routing and scheduling of time-constrained network-on-chip communication. In Proc. DSD, 2006.
20. D. Wingard and A. Kurosawa. Integration architecture for system-on-a-chip design. In Proc. CICC, 1998.
21. H. Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proc. IEEE, 83(10), 1995.