COP: To compress and protect main memory

Proceedings - International Symposium on Computer Architecture

Volumn 13-17-June-2015, Issue , 2015, Pages 682-693

  Palframan, David J ^a   Kim, Nam Sung ^a   Lipasti, Mikko H ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL STORAGE; ERROR CORRECTION; ERRORS; INCOMPRESSIBLE FLOW; MEMORY ARCHITECTURE; METADATA; RADIATION HARDENING;

BLOCK-LEVEL COMPRESSIONS; COMPRESSED DATUM; ERROR CORRECTING CODE; MEMORY ACCESS; MEMORY MODULES; MEMORY SPACE; SOFT ERROR RATE; STORAGE OVERHEAD;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84960117680     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2749469.2750377     Document Type: Conference Paper

References (23)

1. A. Alameldeen and D. Wood, "Adaptive cache compression for highperformance processors," in Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on, June 2004, pp. 212-223.
2. American National Standard for Information Systems, "Coded character sets-7-bit American national standard code for information interchange (7-bit ASCII)," March 1986.
3. R. Baumann, "Soft errors in advanced computer systems," Design Test of Computers, IEEE, vol. 22, no. 3, pp. 258-266, May 2005.
4. C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The PARSEC benchmark suite: Characterization and architectural implications," in Proc. 17th Int. Conf. on Parallel Architectures and Compilation Techniques. New York, NY, USA: ACM, 2008, pp. 72-81.
5. T. E. Carlson, W. Heirman, and L. Eeckhout, "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation," in Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, ser. SC '11. New York, NY, USA: ACM, 2011, pp. 52:1-52:12.
6. L. Chen, Y. Cao, and Z. Zhang, "Free ecc: An efficient error protection for compressed last-level caches," in Computer Design (ICCD), 2013 IEEE 31st International Conference on, Oct 2013, pp. 278-285.
7. T. J. Dell, "A white paper on the benefits of chipkill-correct ecc for pc server main memory," IBM Microelectronics Division, pp. 1-23, 1997.
8. D. Genbrugge, S. Eyerman, and L. Eeckhout, "Interval simulation: Raising the level of abstraction in architectural simulation," in Proc. 16th IEEE Int. Symp. on High Performance Computer Architecture (HPCA), Jan 2010, pp. 1-12.
9. M. Hsiao, "A class of optimal minimum odd-weight-column sec-ded codes," IBM Journal of Research and Development, vol. 14, no. 4, pp. 395-401, 1970.
10. A. Jas and N. Touba, "Test vector decompression via cyclical scan chains and its application to testing core-based designs," in International Test Conference, Oct 1998, pp. 458-464.
11. S. Li, K. Chen, M.-Y. Hsieh, N. Muralimanohar, C. D. Kersey, J. B. Brockman, A. F. Rodrigues, and N. P. Jouppi, "System implications of memory reliability in exascale computing," in Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis. New York, NY, USA: ACM, 2011, pp. 46:1-46:12.
12. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood, "Pin: Building customized program analysis tools with dynamic instrumentation," SIGPLAN Not., vol. 40, no. 6, pp. 190-200, Jun. 2005.
13. S. S. Mukherjee, J. Emer, and S. K. Reinhardt, "The soft error problem: An architectural perspective," in Proc. 11th Int. Symp. on High-Performance Computer Architecture. Washington, DC, USA: IEEE Computer Society, 2005, pp. 243-247.
14. G. Pekhimenko, V. Seshadri, Y. Kim, H. Xin, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, "Linearly compressed pages: A lowcomplexity, low-latency main memory compression framework," in Proc. 46th Annual IEEE/ACM Int. Symp. on Microarchitecture. New York, NY, USA: ACM, 2013, pp. 172-184.
15. G. Pekhimenko, V. Seshadri, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, "Base-delta-immediate compression: Practical data compression for on-chip caches," in Proc. 21st Int. Conf. on Parallel Architectures and Compilation Techniques. New York, NY, USA: ACM, 2012, pp. 377-388.
16. E. Perelman, G. Hamerly, M. Van Biesbrouck, T. Sherwood, and B. Calder, "Using simpoint for accurate and efficient simulation," SIGMETRICS Perform. Eval. Rev., vol. 31, no. 1, pp. 318-319, June 2003.
17. P. Rosenfeld, E. Cooper-Balis, and B. Jacob, "Dramsim2: A cycle accurate memory system simulator," Computer Architecture Letters, vol. 10, no. 1, pp. 16-19, Jan 2011.
18. A. Shafiee, M. Taassori, R. Balasubramonian, and A. Davis, "MemZip: Exploring unconventional benefits from memory compression," in Proc. 20th International Symposium on High Performance Computer Architecture, Feb 2014, pp. 638-649.
19. V. Sridharan and D. Liberty, "A study of DRAM failures in the field," in Proc. of the Int. Conf. on High Performance Computing, Networking, Storage and Analysis. Los Alamitos, CA, USA: IEEE Computer Society Press, 2012, pp. 76:1-76:11.
20. H. Stracovsky, M. Espig, V. W. Lee, and D. Kim, "Reliability support in memory systems without error correcting code support," July 2013, US Patent 8,495,464.
21. J. Suh, M. Manoochehri, M. Annavaram, and M. Dubois, "Soft error benchmarking of l2 caches with PARMA," SIGMETRICS Perform. Eval. Rev., vol. 39, no. 1, pp. 85-96, June 2011.
22. D. H. Yoon and M. Erez, "Virtualized and flexible ecc for main memory," in Proc. Architectural Support for Programming Languages and Operating Systems. New York, NY, USA: ACM, 2010, pp. 397-408.
23. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu, "Minirank: Adaptive DRAM architecture for improving memory power efficiency," in Proc. 41st IEEE/ACM International Symposium on Microarchitecture, Nov 2008, pp. 210-221.