Linearly compressed pages: A low-complexity, low-latency main memory compression framework

MICRO 2013 - Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

Volumn , Issue , 2013, Pages 172-184

  Pekhimenko, Gennady ^a   Seshadri, Vivek ^a   Kim, Yoongu ^a   Xin, Hongyi ^a   Mutlu, Onur ^a   Gibbons, Phillip B ^b   Kozuch, Michael A ^b   Mowry, Todd C ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

data compression; DRAM; memory; memory bandwidth; memory capacity; memory controller

Indexed keywords

BASELINE SYSTEMS; COMPRESSION ALGORITHMS; DEGRADING SYSTEM; MAIN-MEMORY COMPRESSION; MEMORY BANDWIDTHS; MEMORY CAPACITY; MEMORY CONTROLLER; PERFORMANCE DEGRADATION;

ALGORITHMS; BENCHMARKING; COMPUTER ARCHITECTURE; CONTROLLERS; DATA COMPRESSION; DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; PROGRAM PROCESSORS;

CACHE MEMORY;

EID: 84892541151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2540708.2540724     Document Type: Conference Paper

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