A study of DRAM failures in the field

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Volumn , Issue , 2012, Pages

  Sridharan, Vilas ^a   Liberty, Dean ^a  

^a AMD Inc   (United States)

Author keywords

DRAM; hard error; memory; reliability; single event upset; soft error

Indexed keywords

DYNAMIC RANDOM ACCESS MEMORY; ERROR CORRECTING CODE; HARD ERRORS; HIGH-PERFORMANCE COMPUTING CLUSTERS; INTERNAL CIRCUITRY; MODERN COMPUTER SYSTEMS; SINGLE EVENT UPSETS; SOFT ERROR;

CLUSTER COMPUTING; DATA STORAGE EQUIPMENT; ERRORS; FAILURE MODES; RELIABILITY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84877721508     PISSN: 21674329     EISSN: 21674337     Source Type: Conference Proceeding    
DOI: 10.1109/SC.2012.13     Document Type: Conference Paper

References (29)

1. James F. Ziegler and William A. Lanford, "The Effect of Sea Level Cosmic Rays on Electronic Devices," in IEEE International Solid-State Circuits Conference, 1980, pp. 70-71.
2. ITRS, "International Technology Roadmap for Semiconductors," 2010.
3. Bianca Schroeder and Garth A. Gibson, "A Large-Scale Study of Failures in High-Performance Computing Systems," in Proceedings of the International Conference on Dependable Systems and Networks, June, 2006, pp. 249-258.
4. Bianca Schroeder, Eduardo Pinheiro, and Wolf-Dietrich Weber, "DRAM Errors in the Wild: A Large-Scale Field Study," in Proceedings of the 11th Internation Joint Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Seattle, WA, June, 2009.
5. Xin Li, Kai Shen, Michael C. Huang, and Lingkun Chu, "A Memory Soft Error Measurement on Production Systems," in Proceedings of the USENIX Annual Technical Conference, Santa Clara, CA, 2007, pp. 275-280.
6. Abdallah M. Saleh, Juan J. Serrano, and Janak H. Patel, "Reliability of Scrubbing Recovery Techniques for Memory Systems," IEEE Transactions on Reliability, vol. 39, no. 1, pp. 114-122, April 1990.
7. Shubhendu S. Mukherjee, Joel Emer, Tryggve Fossum, and Steven K. Reinhardt, "Cache Scrubbing in Microprocessors: Myth or Necessity?," in Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), March, 2004, pp. 37-42.
8. Timothy J. Dell, "A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory," IBM Corporation, 1997.
9. Algirdas Avizenis, Jean-Claude. Laprie, Brian Randell, and Carl Landwehr, "Basic Concepts and Taxonomy of Dependable and Secure Computing," IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 1, pp. 11-33, Jan-March 2004.
10. Cristian Constantinescu, "Impact of Deep Submicron Technology on Dependenability of VLSI Circuits," in International Conference on Dependable Systems and Networks (DSN), Bethesda, MD, 2002, pp. 205-209.
11. Robert Baumann, "Soft Errors in Advanced Computer Systems," in IEEE Design and Test of Computers, May 2005, pp. 258-266.
12. Cristian Constantinescu, "Trends and Challenges in VLSI Circuit Reliability," IEEE Micro, vol. 23, no. 4, pp. 14-19, July-August 2003.
13. Christopher Weaver, Joel Emer, Shubhendu Mukherjee, and Steven Reinhardt, "Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor," in International Symposium on Computer Architecture (ISCA), Munchen, 2004.
14. Shubhendu Mukherjee, Christopher Weaver, Joel Emer, Steven Reinhardt, and Todd Austin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," in International Symposium on Microarchitecture (MICRO-36), San Diego, 2003.
15. Xin Li, Michael C. Huang, Kai Shen, and Lingkun Chu, "A Realistic Evaluation of Memory Hardware Errors and Software System Susceptibility," in USENIX, Boston, MA, 2010.
16. Andy A. Hwang, Ioan Stefanovici, and Bianca Schroeder, "Cosmic Rays Don't Strike Twice: Understanding the Nature of DRAM Errors and the Implications for System Design," in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), London, 2012.
17. Vilas Sridharan and Dean Liberty, "A Study of DRAM Errors in the Field," in Silicon Errors in Logic - System Effects (SELSE), Champaign, IL, 2012.
18. Bianca Schroeder, Personal Communication.
19. Timothy C. May and Murray H. Woods, "Alpha-Particle Induced Soft Errors in Dynamic Memories," IEEE Transactions on Electron Devices, vol. 26, no. 1, pp. 2-9, January 1979.
20. Alan Messer et al., "Susceptibility of Commodity Systems and Software to Memory Soft Errors," IEEE Transactions on Computers, vol. 53, no. 12, December 2004.
21. Ludger Borucki, Guenter Schindlbeck, and Charles Slayman, "Comparison of Accelerated DRAM Soft Error Rates Measured at Component and System Level," in Reliability Physics Symposium (IRPS), Phoenix, 2008, pp. 482-487.
22. Heather Quinn, Paul Graham, and Tom Fairbanks, "SEEs Induced by High-Energy Protons and Neutrons in SDRAM," in Proceedings of the IEEE Radiation Effects Data Workshop (REDW), Las Vegas, NV, 2011, pp. 1-5.
23. Aniruddha N. Udipi et al., "Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores," in Proceedings of the International Symposium on Computer Architecture (ISCA), Saint-Malo, 2010.
24. Richard W. Hamming, "Error Detecting and Error Correcting Codes," Bell System Technology Journal, vol. 29, no. 2, pp. 147-160, 1950.
25. AMD, Inc., "AMD64 Architecture Programmer's Manual Revision 3.17," 2011.
26. Tom Anderson and Brian Randell, Computing Systems Reliability. Cambridge: Cambridge University Press, 1979.
27. AMD, Inc. (2010, April) BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors. [Online]. http://support.amd.com/us/Processor-TechDocs/ 31116.pdf
28. Doe Hyun Yoon and Mattan Erez, "Virtualized and Flexible ECC for Main Memory," in Architectural Support for Programming Languages and Operating Systems (ASPLOS), Pittsburgh, PA, 2010.
29. Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, and Norman P. Jouppi, "LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems," in ISCA: International Symposium on Computer Architecture, Portland, OR, 2012.