-
3
-
-
84960136796
-
-
"IntelR itaniumR architecture developer's manual, vol. 2," http://www.intel.com/content/www/us/en/processors/itanium/itanium-architecture-s-oftware-developer-rev-2-3-vol-2-manual. html.
-
IntelR ItaniumR Architecture Developer's Manual
, vol.2
-
-
-
5
-
-
84960129157
-
-
"TCMalloc," http://goog-perftools.sourceforge.net/doc/tcmalloc.html.
-
TCMalloc
-
-
-
7
-
-
33744484309
-
BioBench: A benchmark suite of bioinformatics applications
-
K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung, "BioBench: A Benchmark Suite of Bioinformatics Applications," in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005, pp. 2-9, 2005.
-
(2005)
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software
, vol.2005
, pp. 2-9
-
-
Albayraktaroglu, K.1
Jaleel, A.2
Wu, X.3
Franklin, M.4
Jacob, B.5
Tseng, C.-W.6
Yeung, D.7
-
8
-
-
77955012281
-
Translation caching: Skip, don't walk (the page table)
-
T. W. Barr, A. L. Cox, and S. Rixner, "Translation Caching: Skip, Don'T Walk (the Page Table)," in Proceedings of the 37th Annual International Symposium on Computer Architecture, pp. 48-59, 2010.
-
(2010)
Proceedings of the 37th Annual International Symposium on Computer Architecture
, pp. 48-59
-
-
Barr, T.W.1
Cox, A.L.2
Rixner, S.3
-
9
-
-
80052550145
-
Spectlb: A mechanism for speculative address translation
-
T. W. Barr, A. L. Cox, and S. Rixner, "SpecTLB: A Mechanism for Speculative Address Translation," in Proceedings of the 38th Annual International Symposium on Computer Architecture, pp. 307-318, 2011.
-
(2011)
Proceedings of the 38th Annual International Symposium on Computer Architecture
, pp. 307-318
-
-
Barr, T.W.1
Cox, A.L.2
Rixner, S.3
-
10
-
-
84881179047
-
Efficient virtual memory for big memory servers
-
A. Basu, J. Gandhi, J. Chang, M. D. Hill, and M. M. Swift, "Efficient Virtual Memory for Big Memory Servers," in Proceedings of the 40th Annual International Symposium on Computer Architecture, pp. 237-248, 2013.
-
(2013)
Proceedings of the 40th Annual International Symposium on Computer Architecture
, pp. 237-248
-
-
Basu, A.1
Gandhi, J.2
Chang, J.3
Hill, M.D.4
Swift, M.M.5
-
11
-
-
84864859089
-
Reducing memory reference energy with opportunistic virtual caching
-
A. Basu, M. D. Hill, and M. M. Swift, "Reducing Memory Reference Energy with Opportunistic Virtual Caching," in Proceedings of the 39th Annual International Symposium on Computer Architecture, pp. 297-308, 2012.
-
(2012)
Proceedings of the 39th Annual International Symposium on Computer Architecture
, pp. 297-308
-
-
Basu, A.1
Hill, M.D.2
Swift, M.M.3
-
13
-
-
79955889568
-
Shared Last-level TLBs for Chip Multiprocessors
-
A. Bhattacharjee, D. Lustig, and M. Martonosi, "Shared Last-level TLBs for Chip Multiprocessors," in Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture, pp. 62-63, 2011.
-
(2011)
Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture
, pp. 62-63
-
-
Bhattacharjee, A.1
Lustig, D.2
Martonosi, M.3
-
16
-
-
0024860162
-
Translation lookaside buffer consistency: A software approach
-
D. L. Black, R. F. Rashid, D. B. Golub, and C. R. Hill, "Translation Lookaside Buffer Consistency: A Software Approach," in Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 113-122, 1989.
-
(1989)
Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 113-122
-
-
Black, D.L.1
Rashid, R.F.2
Golub, D.B.3
Hill, C.R.4
-
17
-
-
67650067286
-
Immix: A mark-region garbage collector with space efficiency, fast collection, and mutator performance
-
S. M. Blackburn and K. S. McKinley, "Immix: A Mark-region Garbage Collector with Space Efficiency, Fast Collection, and Mutator Performance," in Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 22-32, 2008.
-
(2008)
Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 22-32
-
-
Blackburn, S.M.1
McKinley, K.S.2
-
18
-
-
84880110432
-
Limitations of partial compaction: Towards practical bounds
-
N. Cohen and E. Petrank, "Limitations of partial compaction: Towards practical bounds," SIGPLAN Not., vol. 48, no. 6, pp. 309-320, 2013.
-
(2013)
SIGPLAN Not
, vol.48
, Issue.6
, pp. 309-320
-
-
Cohen, N.1
Petrank, E.2
-
20
-
-
84934291132
-
Supporting superpages in non-contiguous physical memory
-
Feb
-
Y. Du, M. Zhou, B. Childers, D. Mosse, and R. Melhem, "Supporting superpages in non-contiguous physical memory," in Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, pp. 223-234, Feb 2015.
-
(2015)
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture
, pp. 223-234
-
-
Du, Y.1
Zhou, M.2
Childers, B.3
Mosse, D.4
Melhem, R.5
-
21
-
-
84858791438
-
Clearing the clouds: A study of emerging scale-out workloads on modern hardware
-
M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, "Clearing the Clouds: A Study of Emerging Scale-out Workloads on Modern Hardware," in Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 37-48, 2012.
-
(2012)
Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 37-48
-
-
Ferdman, M.1
Adileh, A.2
Kocberber, O.3
Volos, S.4
Alisafaee, M.5
Jevdjic, D.6
Kaynak, C.7
Popescu, A.D.8
Ailamaki, A.9
Falsafi, B.10
-
22
-
-
84937698544
-
BadgerTrap: A tool to instrument x86-64 TLB misses
-
Sep
-
J. Gandhi, A. Basu, M. D. Hill, and M. M. Swift, "BadgerTrap: A Tool to Instrument x86-64 TLB Misses," SIGARCH Comput. Archit. News, vol. 42, no. 2, pp. 20-23, Sep. 2014.
-
(2014)
SIGARCH Comput. Archit. News
, vol.42
, Issue.2
, pp. 20-23
-
-
Gandhi, J.1
Basu, A.2
Hill, M.D.3
Swift, M.M.4
-
23
-
-
84937691489
-
Efficient memory virtualization: Reducing dimensionality of nested page walks
-
J. Gandhi, A. Basu, M. D. Hill, and M. M. Swift, "Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks," in MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 178-189, 2014.
-
(2014)
MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 178-189
-
-
Gandhi, J.1
Basu, A.2
Hill, M.D.3
Swift, M.M.4
-
24
-
-
84858767550
-
A case for unlimited watchpoints
-
J. L. Greathouse, H. Xin, Y. Luo, and T. Austin, "A Case for Unlimited Watchpoints," in Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 159-172, 2012.
-
(2012)
Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 159-172
-
-
Greathouse, J.L.1
Xin, H.2
Luo, Y.3
Austin, T.4
-
25
-
-
36849034066
-
SPEC CPU2006 Benchmark Descriptions
-
Sep
-
J. L. Henning, "SPEC CPU2006 Benchmark Descriptions," SIGARCH Comput. Archit. News, vol. 34, no. 4, pp. 1-17, Sep. 2006.
-
(2006)
SIGARCH Comput. Archit. News
, vol.34
, Issue.4
, pp. 1-17
-
-
Henning, J.L.1
-
29
-
-
0032119566
-
Virtual memory in contemporary microprocessors
-
Jul
-
B. Jacob and T. Mudge, "Virtual Memory in Contemporary Microprocessors," IEEE Micro, vol. 18, no. 4, pp. 60-75, Jul. 1998.
-
(1998)
IEEE Micro
, vol.18
, Issue.4
, pp. 60-75
-
-
Jacob, B.1
Mudge, T.2
-
31
-
-
84946036877
-
Performance analysis of the memory management unit under scale-out workloads
-
V. Karakostas, O. S. Unsal, M. Nemirovsky, A. Cristal, and M. Swift, "Performance Analysis of the Memory Management Unit under Scale-out Workloads," in Proceedings of the 2014 IEEE International Symposium on Workload Characterization, pp. 1-12, 2014.
-
(2014)
Proceedings of the 2014 IEEE International Symposium on Workload Characterization
, pp. 1-12
-
-
Karakostas, V.1
Unsal, O.S.2
Nemirovsky, M.3
Cristal, A.4
Swift, M.5
-
33
-
-
1842522705
-
Design of the b 5000 system
-
May
-
W. Lonehgan and P. King, "Design of the b 5000 system," Datamation, vol. 7, no. 5, May 1961.
-
(1961)
Datamation
, vol.7
, Issue.5
-
-
Lonehgan, W.1
King, P.2
-
34
-
-
84878619560
-
TLB improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level tlbs
-
Apr
-
D. Lustig, A. Bhattacharjee, and M. Martonosi, "TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs," ACM Trans. Archit. Code Optim., vol. 10, no. 1, pp. 2:1-2:38, Apr. 2013.
-
(2013)
ACM Trans. Archit. Code Optim.
, vol.10
, Issue.1
, pp. 21-238
-
-
Lustig, D.1
Bhattacharjee, A.2
Martonosi, M.3
-
36
-
-
84978389801
-
Practical, transparent operating system support for superpages
-
J. Navarro, S. Iyer, P. Druschel, and A. Cox, "Practical, Transparent Operating System Support for Superpages," in Proceedings of the 5th Symposium on Operating Systems Design and implementation, pp. 89-104, 2002.
-
(2002)
Proceedings of the 5th Symposium on Operating Systems Design and Implementation
, pp. 89-104
-
-
Navarro, J.1
Iyer, S.2
Druschel, P.3
Cox, A.4
-
37
-
-
84934289942
-
Prediction-based superpage-friendly TLB designs
-
Feb
-
M.-M. Papadopoulou, X. Tong, A. Seznec, and A. Moshovos, "Prediction-based superpage-friendly TLB designs," in Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, pp. 210-222, Feb 2015.
-
(2015)
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture
, pp. 210-222
-
-
Papadopoulou, M.-M.1
Tong, X.2
Seznec, A.3
Moshovos, A.4
-
38
-
-
84903973894
-
Increasing TLB reach by exploiting clustering in page translations
-
B. Pham, A. Bhattacharjee, Y. Eckert, and G. H. Loh, "Increasing TLB reach by exploiting clustering in page translations," in Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, pp. 558-567, 2014.
-
(2014)
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture
, pp. 558-567
-
-
Pham, B.1
Bhattacharjee, A.2
Eckert, Y.3
Loh, G.H.4
-
39
-
-
84876544775
-
CoLT: Coalesced large-reach TLBs
-
B. Pham, V. Vaidyanathan, A. Jaleel, and A. Bhattacharjee, "CoLT: Coalesced Large-Reach TLBs," in Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 258-269, 2012.
-
(2012)
Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 258-269
-
-
Pham, B.1
Vaidyanathan, V.2
Jaleel, A.3
Bhattacharjee, A.4
-
41
-
-
84960097971
-
-
D. Quintero, S. Chabrolles, C. H. Chen, M. Dhandapani, T. Holloway, C. Jadhav, S. K. Kim, S. Kurian, B. Raj, R. Resende, B. Roden, N. Srinivasan, R. Wale, W. Zanatta, and Z. Zhang, "IBM Power Systems Performance Guide Implementing and Optimizing," 2013.
-
(2013)
IBM Power Systems Performance Guide Implementing and Optimizing
-
-
Quintero, D.1
Chabrolles, S.2
Chen, C.H.3
Dhandapani, M.4
Holloway, T.5
Jadhav, C.6
Kim, S.K.7
Kurian, S.8
Raj, B.9
Resende, R.10
Roden, B.11
Srinivasan, N.12
Wale, R.13
Zanatta, W.14
Zhang, Z.15
-
42
-
-
0033707299
-
Recency-based TLB preloading
-
A. Saulsbury, F. Dahlgren, and P. Stenström, "Recency-based TLB Preloading," in Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 117-127, 2000.
-
(2000)
Proceedings of the 27th Annual International Symposium on Computer Architecture
, pp. 117-127
-
-
Saulsbury, A.1
Dahlgren, F.2
Stenström, P.3
-
44
-
-
84859717032
-
Sparc T4: A dynamically threaded server-on-a-chip
-
Mar
-
M. Shah, R. Golla, G. Grohoski, P. Jordan, J. Barreh, J. Brooks, M. Greenberg, G. Levinsky, M. Luttrell, C. Olson, Z. Samoail, M. Smittle, and T. Ziaja, "Sparc T4: A Dynamically Threaded Server-on-a-Chip," IEEE Micro, vol. 32, no. 2, pp. 8-19, Mar. 2012.
-
(2012)
IEEE Micro
, vol.32
, Issue.2
, pp. 8-19
-
-
Shah, M.1
Golla, R.2
Grohoski, G.3
Jordan, P.4
Barreh, J.5
Brooks, J.6
Greenberg, M.7
Levinsky, G.8
Luttrell, M.9
Olson, C.10
Samoail, Z.11
Smittle, M.12
Ziaja, T.13
-
48
-
-
66749131884
-
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
-
M. Tiwari, B. Agrawal, S. Mysore, J. Valamehr, and T. Sherwood, "A Small Cache of Large Ranges: Hardware Methods for Efficiently Searching, Storing, and Updating Big Dataflow Tags," in Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, pp. 94-105, 2008.
-
(2008)
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 94-105
-
-
Tiwari, M.1
Agrawal, B.2
Mysore, S.3
Valamehr, J.4
Sherwood, T.5
-
49
-
-
0036957412
-
Mondrian memory protection
-
E. Witchel, J. Cates, and K. Asanovíc, "Mondrian Memory Protection," in Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 304-316, 2002.
-
(2002)
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 304-316
-
-
Witchel, E.1
Cates, J.2
Asanovíc, K.3
-
50
-
-
0022583630
-
An in-cache address translation mechanism
-
D. A. Wood, S. J. Eggers, G. Gibson, M. D. Hill, and J. M. Pendleton, "An In-cache Address Translation Mechanism," in Proceedings of the 13th Annual International Symposium on Computer Architecture, pp. 358-365, 1986.
-
(1986)
Proceedings of the 13th Annual International Symposium on Computer Architecture
, pp. 358-365
-
-
Wood, D.A.1
Eggers, S.J.2
Gibson, G.3
Hill, M.D.4
Pendleton, J.M.5
|