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Volumn 13-17-June-2015, Issue , 2015, Pages 66-78

Redundant memory mappings for fast access to large memories

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COST REDUCTION; HARDWARE; MAPPING; RECONFIGURABLE HARDWARE; SOFTWARE PROTOTYPING;

EID: 84960085139     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2749469.2749471     Document Type: Conference Paper
Times cited : (138)

References (50)
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    • Cohen, N.1    Petrank, E.2
  • 22
    • 84937698544 scopus 로고    scopus 로고
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    • Sep
    • J. Gandhi, A. Basu, M. D. Hill, and M. M. Swift, "BadgerTrap: A Tool to Instrument x86-64 TLB Misses," SIGARCH Comput. Archit. News, vol. 42, no. 2, pp. 20-23, Sep. 2014.
    • (2014) SIGARCH Comput. Archit. News , vol.42 , Issue.2 , pp. 20-23
    • Gandhi, J.1    Basu, A.2    Hill, M.D.3    Swift, M.M.4
  • 25
    • 36849034066 scopus 로고    scopus 로고
    • SPEC CPU2006 Benchmark Descriptions
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    • J. L. Henning, "SPEC CPU2006 Benchmark Descriptions," SIGARCH Comput. Archit. News, vol. 34, no. 4, pp. 1-17, Sep. 2006.
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    • Henning, J.L.1
  • 29
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    • B. Jacob and T. Mudge, "Virtual Memory in Contemporary Microprocessors," IEEE Micro, vol. 18, no. 4, pp. 60-75, Jul. 1998.
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    • W. Lonehgan and P. King, "Design of the b 5000 system," Datamation, vol. 7, no. 5, May 1961.
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    • TLB improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level tlbs
    • Apr
    • D. Lustig, A. Bhattacharjee, and M. Martonosi, "TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs," ACM Trans. Archit. Code Optim., vol. 10, no. 1, pp. 2:1-2:38, Apr. 2013.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.