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Volumn , Issue , 2007, Pages 59-62

Bitwise competition logic for compact digital comparator

Author keywords

[No Author keywords available]

Indexed keywords

COMPETITION; DIGITAL ARITHMETIC; ELECTRIC LOAD MANAGEMENT;

EID: 51349145631     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425682     Document Type: Conference Paper
Times cited : (51)

References (11)
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    • David G. Lowe, "Object Recognition from Local Scale-Invariant Features," IEEE International Confernce on Computer Vision, pp. 1150-1157, Sept. 1999
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    • Lowe, D.G.1
  • 4
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    • A Low-Power 3-D Rendering Engine With Two Texture Units and 29-Mb Embedded DRAM for 3G Multimedia Terminals
    • July
    • Ramchan Woo, et al., "A Low-Power 3-D Rendering Engine With Two Texture Units and 29-Mb Embedded DRAM for 3G Multimedia Terminals," IEEE Journal of Solid-State Circuits, vol. 39, no.7, pp. 1101-1109, July 2004.
    • (2004) IEEE Journal of Solid-State Circuits , vol.39 , Issue.7 , pp. 1101-1109
    • Woo, R.1
  • 5
    • 0032201772 scopus 로고    scopus 로고
    • 1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking
    • Nov
    • C.-C Wang, C.-F. Wu, and K.-C. Tsai, "1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking," IEEE Proceedings of Computers and Digital Techniques, vol. 145, issue 6, pp. 433-436, Nov. 1998
    • (1998) IEEE Proceedings of Computers and Digital Techniques , vol.145 , Issue.6 , pp. 433-436
    • Wang, C.-C.1    Wu, C.-F.2    Tsai, K.-C.3
  • 6
    • 0037323076 scopus 로고    scopus 로고
    • High-Performance and Power-Efficient CMOS Comparators
    • Feb
    • C.-H Huang and J.-S. Wang, "High-Performance and Power-Efficient CMOS Comparators," IEEE Journal of Solid State Circuit, vol. 38, issue 2, pp. 254-262, Feb. 2003
    • (2003) IEEE Journal of Solid State Circuit , vol.38 , Issue.2 , pp. 254-262
    • Huang, C.-H.1    Wang, J.-S.2
  • 9
    • 0036474883 scopus 로고    scopus 로고
    • Race logic architecture (RALA): A novel logic concept using the race scheme of input variables
    • Feb
    • Se-Joong Lee and Hoi-Jun Yoo, "Race logic architecture (RALA): a novel logic concept using the race scheme of input variables," IEEE Journal of Solid-State Circuits, vol. 37, issue 2, pp. 191-201, Feb. 2002
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , Issue.2 , pp. 191-201
    • Lee, S.-J.1    Yoo, H.-J.2
  • 10
    • 51349138565 scopus 로고    scopus 로고
    • Semiconductor Industry Association, National Technology Roadmap for Semiconductors
    • Semiconductor Industry Association, National Technology Roadmap for Semiconductors 1997
    • (1997)
  • 11
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • IEEE Micro, Iisue 4, pp, Jul.-Aug
    • Shekhar Borkar, "Design challenges of technology scaling", IEEE Micro, vol. 19, Iisue 4, pp. 23-29, Jul.-Aug. 1999
    • (1999) , vol.19 , pp. 23-29
    • Borkar, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.