Shared last-level TLBs for chip multiprocessors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 62-73

  Bhattacharjee, Abhishek ^a   Lustig, Daniel ^b   Martonosi, Margaret ^b  

^a RUTGERS UNIVERSITY   (United States)

^b Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSOR; MISS-RATE; PROCESSOR PERFORMANCE; RUNTIMES; SEQUENTIAL APPLICATIONS; TRANSLATION LOOKASIDE BUFFER; UNIPROCESSORS;

BUFFER STORAGE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; MULTIPROGRAMMING;

COMPUTER ARCHITECTURE;

EID: 79955889568     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749717     Document Type: Conference Paper

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