SpecTLB: A mechanism for speculative address translation

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 307-317

  Barr, Thomas W ^a   Cox, Alan L ^a   Rixner, Scott ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

Memory management; TLB

Indexed keywords

ADDRESS TRANSLATION; DATA-INTENSIVE COMPUTING; MEMORY MANAGEMENT; MISS-RATE; NOVEL DEVICES; PAGE TABLE; PHYSICAL MEMORY; PRE-FETCHING SCHEME; SPECULATIVE EXECUTION; TLB; VIRTUAL MEMORY SYSTEMS;

DISTRIBUTED COMPUTER SYSTEMS; INFORMATION MANAGEMENT; MEMORY ARCHITECTURE; STORAGE ALLOCATION (COMPUTER); COMPUTER ARCHITECTURE;

BUFFER STORAGE; DISTRIBUTED COMPUTER SYSTEMS;

EID: 80052550145     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000101     Document Type: Conference Paper

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