A reconfigurable shared scan-in architecture

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 9-14

  Samaranayake, S ^a   Gizdarski, E ^b   Sitchinava, N ^a   Neuveux, F ^b   Kapur, R ^b   Williams, T W ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Automatic test pattern generation; Broadcasting; Circuit faults; Circuit synthesis; Circuit testing; Costs; Electrical fault detection; Fault detection; Flip flops; Logic testing

Indexed keywords

BROADCASTING; CHAINS; COSTS; DATA COMPRESSION; ELECTRIC FAULT LOCATION; FAULT DETECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; RECONFIGURABLE ARCHITECTURES; SEQUENTIAL CIRCUITS; SYNTHESIS (CHEMICAL); TOPOLOGY; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT SYNTHESIS; CIRCUIT TESTING; ELECTRICAL FAULT DETECTIONS; LOGIC TESTING;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84943541993     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197627     Document Type: Conference Paper

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