Fault set partition for efficient width compression

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 194-199

  Gizdarski, E ^a   Fujiwara, H ^b  

^a SYNOPSYS INC   (United States)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Automatic testing; Benchmark testing; Built in self test; Circuit faults; Circuit testing; Counting circuits; Decoding; Logic testing; Pulse inverters; Test pattern generators

Indexed keywords

AUTOMATIC TESTING; BINS; COUNTING CIRCUITS; DECODING; ECONOMIC AND SOCIAL EFFECTS; INTEGRATED CIRCUIT TESTING;

BENCHMARK TESTING; CIRCUIT FAULTS; CIRCUIT TESTING; LOGIC TESTING; PULSE INVERTERS; TEST PATTERN GENERATOR;

BUILT-IN SELF TEST;

EID: 33746897084     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181710     Document Type: Conference Paper

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