Dynamic scan: Driving down the cost of test

Computer

Volumn 35, Issue 10, 2002, Pages 63-68

  Samaranayake, Samitha ^a   Sitchinava, Nodari ^a   Kapur, Rohit ^b   Amin, Minesh B ^b   Williams, Thomas W ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; DYNAMIC SCAN;

ALGORITHMS; COMPUTER ARCHITECTURE; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING;

AUTOMATIC TESTING;

EID: 0036794893     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2002.1039519     Document Type: Article

References (7)

1. V.D. Agrawal, S.K. Jain, and D. Singer, "A CAD System for Design for Testability," VLSI Design, Oct. 1984, pp. 46-54.
2. S.P. Morley and R.A. Marlett, "Selectable Length Partial Scan: A Method to Reduce Vector Length," Proc. Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1991, pp. 385-392.
3. S. Narayanan and M. Breuer, "Reconfiguration Techniques for a Single Scan Chain," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 6, pp. 750-765.
4. S. Narayanan, R. Gupta, and M.A. Breuer, "Optimal Configuring of Multiple Scan Chains," IEEE Trans. Computers, vol. 42, no. 9, pp. 1121-1131.
5. I. Hamzaoglu and J.H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. 29th Int'l Symp. Fault-Tolerant Computing (FTCS 99), IEEE CS Press, Los Alamitos, Calif., 1999, pp. 260-267.
6. G. Karypis and V. Kumar, hMetis 1.5: A Hypergraph Partitioning Package, tech. report, Dept. Computer Science, Univ. of Minn., 1998; http://www.cs.umn.edu/-metis.
7. G. Karypis and V. Kumar, Multilevel k-way Hypergraph Partitioning, tech. report, Dept. Computer Science, Univ. of Minn., 1998; http://www.cs.umn.edu/-metis.