A 1.2 v 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective I/O test circuits

IEEE Journal of Solid-State Circuits

Volumn 50, Issue 1, 2015, Pages 191-203

  Lee, Dong Uk ^a   Kim, Kyung Whan ^a   Kim, Kwan Weon ^a   Lee, Kang Seol ^a   Byeon, Sang Jin ^a   Kim, Jae Hwan ^a   Cho, Jin Hee ^a   Lee, Jaejin ^a   Chun, Jun Hyun ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

Built in self test; calibration; chip on wafer; DRAM; known good stack; loopback; microbump; PHY; stacked memory; TSV

Indexed keywords

BANDWIDTH; BUILT-IN SELF TEST; CALIBRATION; DYNAMIC RANDOM ACCESS STORAGE; VOLTAGE CONTROL;

KNOWN GOOD STACK; LOOPBACK; MICRO-BUMPS; ON-WAFER; PHY; STACKED MEMORY; TSV;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84920169503     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2014.2360379     Document Type: Article

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